Hi,
Could you please help with the following query on the recommended reset assert time for DP83867CS in SGMII mode?
-> We've observed an issue on TI DP83867CS phy reset assert time on one of our boards. We use the open source linux driver and have a 100us reset assert time and 280us reset de-assert time selected in the SW. I can see from the specification that both the reset assert and de-assert times are more than enough as per the specification (1 us and 195us respectively). However, on one of some our boards, we observed a need to increase assert time to 136us or 300us.
-> Further, please note that the times I specified above are the SW delay values requested in Linux. On board, the delay is much higher. For ex., when the reset assert time is specified as 100us in the Linux SW, probing with the phy reset pin with the oscilloscope showed ~308 us of pulse width. Even with this, we noticed that the phy was inaccessible.
-> We have used TI DP83867 on other evaluation boards, in RGMII mode. We observe this issue only on this particular HW (SGMII) so far.
Could you please comment on this behavior and let us know the recommended assert time?
Regards,
Harini
