Hi
I was looking at the DP83869EVM reference design which we are planning to use in one of our application.
In reference design I could see PHY-MDC pin is connected to PM_UCB1SDA and PHY-MDIO pin is connected to PM_UCB1SCL.
I wanted to know is there any particular purpose for this connection, I mean MDC CLK to DATA and MDIO data to SCL CLK.
Why the default signal mapping is not considered here?
Below is the Screenshot of controller section from EVM reference schematics.
Thanks & Regards,
Preethi
