DP83822I: need clarification on 4-level strap voltage ratio

Hi Klaus,

Table 8-9 describes the threshold voltages for debug purposes. These threshold voltages are usually described as ratios of VDDIO since VDDIO can be either 1.8V, 2.5V or 3.3V.
The threshold voltage for each mode means the voltage at which the device stays in that particular mode.
These voltages are mentioned in the datasheet as some customers like to do calculations and measurements to validate that the strap are working fine.

For eg. the PHY stays in Mode2 when pin voltage in reset state stays between 0.148*VDDIO and 0.181*VDDIO.

In short, this is no strap for VDDIO, but rather the threshold voltages (mentioned in multiples of VDDIO) for which a particular strap mode is selected.

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Regards,
Gokul.

Hello, this is clear, but what the the MODEs means. There is not clear definition of the modes as I see. Our issue is this pin we have connected to SD pin of optical transceiver and therefore during startup there can be two different voltage (FO cable pugged / FO cable not plugged). This voltage are actually 0.3V for logical low and 1.24V for logical high during startup because in PHY there is 9k pull down. After the PHY startup correctly there is 0.3V or 1.8V. For the case with connected FO cable  (1.24V) we do not have problem but in case then 0,3V is not connected we have problem because the PHY do not start up. When I see our voltage and calculate the voltage for different modes I see that 0.3V is for MODE2 and 1.24V is for mode4.  SO my question is mainly what are those mode and why in MODE2 (0.3V) PHY did not work and in MODE4 (1.24V]) the PHY is working.

Hi Victor,

Let me discuss this with my team and get back to you in a day.

--
Regards,
Gokul.

Hi Victor,

I want to understand why the voltages are 0.3V and 1.24V when this Signal detect pin (LED_1) is driven by SFP module directly.
Any reason why voltage driven on this pin is not rail-to-rail?

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Regards,
Gokul.

HI, this topic was already in topic "DP83822IF Pin24 signla Detect" where I do not have access. the problem is that the PHy is supply by 1V8 and transceiver is supply by 3V3, so there must be voltage shifter, we make if with BC846BW. So then FO transciever has logical high 3,3V the PHY gets 1,24V because of internal pull down 9k (we have 4k7 pull up permanently connected) , this is ok. but in case of transiever has logical 0, it has actually 0,25V because FO transciever is not rail-to-rail and the PHY ten gets 0,25V or similar and this cause that the PHY goes to the undocumented test mode in datasheet :-(. 

So my main question is what it the exact window what can causes the  PHY will go to undocumented test mode  when PHY is set to MODE3. We need to know low and upper limits to set the values correctly. From the last conversation we see that lower limit shall be 0,098*VDD but that is the upper limits. Is this valid for competed temperature range? When we can expect that this undocumented feature will be officially put to the DS?

In DS is also written that the FO transceiver is possible connect to PHY, but this is very dangerous since the signal detect pins is not define by standard that must be rail-to-rail, so we basically follow your recommendation and designs fail because you have this undocumented feature. :-(

Hi Victor,

The lower limit of 0.098*VDDIO will be applicable for all temperature ranges. So you have ensure that the pin voltage is lower than that across all conditions.

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Regards,
Gokul.

Thank you, can you also provide us what us upper limit to do not got to this undocumented test mode?