TNETE2201B: Spartan-7(XC7S50) Interface with TNETE2201BPJW(1.25-gigabit ethernet transceiver)

N S

Prodigy 50 points

Part Number: TNETE2201B

Dear Forum members

I am working on PCB design Project in which I need to interface Spartan-7(XC7S50) with TNETE2201BPJW(1.25-gigabit ethernet transceiver). Please guide me.

TNETE2201BPJW Datasheet: https://www.ti.com/lit/ds/symlink/tnete2201b.pdf?ts=1688657257170&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTNETE2201B%252Fpart-details%252FTNETE2201BPJW

Spartan-7 Datasheet: https://docs.xilinx.com/v/u/en-US/ds180_7Series_Overview

over 1 year ago

0 Drew Miller1 over 1 year ago

TI__Mastermind 24032 points

Hi,

You will need to configure your FPGA to encode/decode 8b/10b data and transmit/receive the data over a parallel interface. You will also need to provide the device with a 125 MHz reference clock that is synchronous TD[9:0]. Additionally, you will need to periodically transmit K28.5 comma characters in order to synchronize the receiver and align the data.

Please let us know if you have additional specific questions or concerns in implementing this device.

Thanks,

Drew

0 N S over 1 year ago in reply to Drew Miller1

Prodigy 50 points

Do you have any reference designs for TNETE2201B?

0 Drew Miller1 over 1 year ago in reply to N S

TI__Mastermind 24032 points

Hi,

Unfortunately I'm not aware of any reference designs using TNETE2201B. Are there any specific questions you have regarding implementing this device?

Thanks,
Drew

0 N S over 1 year ago in reply to Drew Miller1

Prodigy 50 points

Hi Drew

my FPGA and transceiver connections are like that:

TD[0:9]-> FPGA bank 15 user IO

RD[0:9]-> FPGA bank 15 user IO

RBC0,RBC1, and REFCLK-> MRCC_15 pin

Is this interface correct?

0 Drew Miller1 over 1 year ago in reply to N S

TI__Mastermind 24032 points

Hi,

I wasn't able to locate documentation about the different FPGA pin groups. Can you point me towards this information?

Thanks,

Drew

0 N S over 1 year ago in reply to Drew Miller1

Prodigy 50 points

0 N S over 1 year ago in reply to N S

Prodigy 50 points

Please check the schematic.

+1 Drew Miller1 over 1 year ago in reply to N S

TI__Mastermind 24032 points

Hi,

I reviewed the schematic, please find my notes below:

VCC: Good; A common design practice is to add 0.1uF decoupling capacitor for each VCC pin. Would consider making sure there are at least a couple decoupling capacitors near this device on SERDES_VCC.
DOUT: Rpu Good; Typically see AC coupling of at least 100nF
DIN: Typically see AC coupling of at least 100nF. I would consider deriving Vt from VCC_Rx instead of SERDES_VCC
RC0/1: Good
TC0/1: Good
TD[9:0]: Good
RD[9:0]: Good
LCKREFN, LOOPEN, SYNCEN: Good
RBC0/1: Good
REFCLK: Good
SYNC: Good

Thanks,

Drew

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Interface

Interface forum

TNETE2201B: Spartan-7(XC7S50) Interface with TNETE2201BPJW(1.25-gigabit ethernet transceiver)

Dear Forum members

I am working on PCB design Project in which I need to interface Spartan-7(XC7S50) with TNETE2201BPJW(1.25-gigabit ethernet transceiver). Please guide me.

TNETE2201BPJW Datasheet: https://www.ti.com/lit/ds/symlink/tnete2201b.pdf?ts=1688657257170&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTNETE2201B%252Fpart-details%252FTNETE2201BPJW

Spartan-7 Datasheet: https://docs.xilinx.com/v/u/en-US/ds180_7Series_Overview