DS125DF1610: Signal Detect valid, CDR unlock

Hi Chris,

If the input signal has similar margins through each test case, then this could be a state machine bug resulting from toggling the input signal rapidly.

Is 100ms the average duration of electrical idle between each signal case?

I have two suggestions for now:

1. Disable single bit limit via 0x0C[3] = 0. This parameter may gate CDR lock in the case of toggling the input signal with some delay.

2. In the case of CDR unlock, attempt CDR reset with the following writes:

• 0x0A[3:2] = 2'b11
• 0x0A[3:2] = 2'b00 

Thank you,

Evan

Hi Evan,

Thanks for your quick response. 

In my design, reset is hold for 100ms, then initialization process, so it should be more than 100ms.

In channel register 0x34[6],  By default, all blocks (except signal detect) power down after 100ms after signal detect goes low. 

Will longer time be helpful? I copied the diagram below, If I was using 200ms, then the Digital core, EQ and other blocks should all be power down, is that right? If so the state machine should also be powered down, is that right?

I can't use the reset pin to reset the whole 16 lanes, as I only got this problem with lane 8 (lane number, 0,1..15)

I tried, the 0xA[3:2] = 2'b11 didn't work either。 

For 0x0C[3] bit, in case this error happen again, I'll try with it.

I copied the register of channel 8 when input is EI and normal data below:

----------------channel 8 input is EI, register dump------------------
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 00 00 00 01 01 01 01 60 00 50 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 40 03 78 00 00 00 30 0f f2 00 00 b6
0x30 : 00 38 11 88 bf 1f 30 00 00 00 00 42 4f 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 00 10 00 00 00 48 13 3a
0x80 : 00 e4 00 00 00 00 00 00 00 01 d1 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5

----------------channel 8 input is normal data, register dump------------------
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 00 00 01 01 01 01 60 00 50 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 40 03 78 00 00 00 30 0f f2 00 00 b6
0x30 : 00 38 11 88 bf 1f 30 00 00 00 00 42 4f 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 20 10 00 00 00 48 13 3a
0x80 : 00 e4 00 00 00 00 00 00 00 01 d1 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5

Regards

Chris

Hi Chris,

It's possible the CDR does not have enough time to react to signal detect status.

I suggest attempting the same test case again with 200ms of delay. If this resolves the CDR unlock case, then this delay can be decreased at regular increments until the minimum delay without error is found.

Thank you,

Evan

Actually I tried to control the output of A manually, so the time must be longer than 200ms, at least a few seconds I think, still the same.

I agree with you that something might be wrong when the input signals changed in a small interval, I would change the interval to 200ms and have a try.

This phenomenon only happened once so far, I can't repeat it in 2000+ times, I'll continue with my test, until it happens again. 

I have to keep debugging it, once it happen, I've to reset the whole 16 lanes, it's unacceptable for my design.

Thank you.

Chris

Hi Chris,

Glad to hear you are not experiencing the issue at a high rate. Curious to see the test results with 200ms interval when you are able to share.

Chris Zhao1 said:

I tried, the 0xA[3:2] = 2'b11 didn't work either。 

Did you write 0xA[3:2] = 2'b00 afterwards? The CDR reset sequence will only work when setting bits 0xA[3:2] high to put CDR in reset, then releasing the reset via 0xA[3:2] low to release reset.

Thank you,

Evan

Yes, I set both bits 2'b11, then release them.  Will let you know my new test results with 200ms EI .

Thanks

Chris