Hi Team,
I have attached the Schemtic of DP83867CSRGZ please review and let me know your valuable feedback.
Many Thanks
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Hi Team,
I have attached the Schemtic of DP83867CSRGZ please review and let me know your valuable feedback.
Many Thanks
Hi Rajat,
Please refer to this schematic review checklist to review the pin layout (see "Pin Wise Checklist" tab):
DP83867_Schematic_Design_Review_Checklist.xls
I am able to give further feedback if you have questions beyond the recommendations in this checklist.
Thank you,
Evan
Hi Evan,
Thanks for sharing the checklist ,I have 2 question on shared checklist-
Q1- What will be the RGMII TX and RX clock skew in case of MAC Interface is SGMII?Is there any signigicance of TX and RX Clock skew in SGMII Mode?
Q2-RX_CTRL Pin suggested floating in PIN Wise checklist Tab then How Autoneg Feature will be supported in SGMII mode?
Note- We are using PHY in SGMII Mode
Many Thanks
Rajat
Hi Rajat,
1) TX and RX clock skew is not relevant to SGMII mode
2) RX_CTRL can be strapped to mode 3 if autoneg is desired in SGMII
Thank you,
Evan
Hi Evan,
1)So there is no no need to connect strap Pin (GPIO0,GPIO1,LED2) to Pull up and Pull down in SGMII Mode?Please confirm
2)Okay, I will update it.
Many Thanks
Rajat
Hi Rajat,
1)So there is no no need to connect strap Pin (GPIO0,GPIO1,LED2) to Pull up and Pull down in SGMII Mode?Please confirm
Correct, these pins can be left at default strap values for SGMII.
Thank you,
Evan
Hi Evan,
What is the worst case current number in SGMII Mode for below 2 Powers
1,VDD1P0
2.VDDA2P5
3.VDDIO-1.8V
Many Thanks
Rajat
By not connecting a PU/PD to the pin, it will strap into the default value [00].
Thanks,
Evan
Please refer to the following appnote for worst case power consumption:
https://www.ti.com/lit/an/snla241/snla241.pdf (4.1)
Thank you,
Evan