DP83TC812S-Q1: SGMII Interface

Hello Norio,

I have emailed you

Regards,
Avtar

any update ？we encounter the same problem. When replace DP83TG720 will clear the problem.

Hi Norio,

Thanks for providing this information. We are consulting our designers on this issue at the moment, however we will need some more information from you to find the root cause. 

What percent of CRC errors are you seeing? Are you seeing packet loss too? What percent packet loss?

Best regards,

Melissa

Hi Melissa,

Sorry for the late reply.

(1)At error case, CRC errors occuer 40～50%.  

　For example..

 　PHY RX ER (RECR　0x15) :0

 　uPC detect Received Packet:2441

 　uPC detect  CRC error  : 993

 　CRC error is : 40.6%

(2)Packet loss doesn't seem to be occurring.

Regards, 

Norio

Really ?

If you don't mind, could you tell me the conditions?

(1)DP83TC812-Q1 

   ・IInterface :SGMII  

   ・Speed :100BASE 

　・uPC : RH850( Renesas） or other device ? 

 (2)DP83TG720S-Q1  ??

　 ・IInterface :SGMII?  

 　・Speed :1000BASE ?　（Have you changed your rate?）

Regards,

1) DP83TC812S and DP83TC817S. SGMII 100BASE RH850/U2A16.

2)YES. DP83TG720S. SGMII 1000BASE. The MAC speed have changed to 1000MHz.

Thank you for the information.

Welcome Norio.

Hi Norio Hasegawa，Are you using Renesas RH850 MCU also ?

Hi Norio,

We asked for a picture of the SGMII eye a few weeks back from the outpiut of the PHY. Could you take one?

You just need to take probe RX_P and RX_M pins on an oscilloscope. Then, use the math function to subtract the RX_M channel from the RX_P at infinite persistence. We want to confirm the eye looks clean.

Best regards,

Melissa

Hi Norio Hasegawa ，I am using RH850 also，i try to capture the Ethernet frame with CRC error，but found that RH850 just report CRC error，and do not report the CRC error frame. Question: I saw you can dump the CRC error frame, how you do that ? can you share me that ?

Hi, user6129188

Yes, We are using RH850 U2A16 too !

Ethernet driver is based on starter kit sample code. and midified it.
www.renesas.com/.../y-ask-rh850f1km-s4-v3-rh850f1km-s4-and-rh850f1km-s2-starter-kit

Regards,

Hi Melisa,

OK, I will e-mail some data  to Avtar. 

Regards,

Norio

Hi user6129188,

We check CRC error frame below,

 ETNB1RCR bit0(EFFS) =    ETNB1RCR = 0x1800_000B   (lower word : 0000_1011)

Check Rx Memory and  ETNB1CEFCR,  ETNB1RFCR

Regards.

Hi Norio thank for you kindly help. It work. 

Setup: CANOE(BCM89811) <--------MDI-------> DP83TC817S <----------SGMII-----------> MAC(RH850/U2A16)

TX:12 34 56 78 9A BC DE

RX:10 32 54 76 98 BA DC OE

Hi user6129188,

Thanks your information.

Looks like the same phenomenon!

Regards.

Hi Melissa,

Have you checked the materials?

I would also like the following information. like user6129188.

・ How TI verify DP83TC812S_Q1 SGMII Interface ?

・ Can you list out which DP83TC812S_Q1   SOC/MCU can support to verify SGMII Interface?

Best regards,

Norio.

Hi Norio,

We design and verify the SGMII interface based on the SGMII the specifications. You can find these specs here: https://ia803002.us.archive.org/25/items/sgmii/SGMII.pdf

The DP83TC812 should support any MCU that implements SGMII correctly. We have been testing the DP83TC812 with the TDA4 processor, for instance.

Best regards,

Melissa

Hi Melissa,

Thank you for the information.

(1) Did you find anything out of the materials?

　Other users have also encountered 100BAE SGMII NG, so I don't think it's a problem with the circuit or pattern.

　Is there any way to investigate the problem? Can you give me some more advice?　

(2) Renesas Microcontrollers 

＞The DP83TC812 should support any MCU that implements SGMII correctly

　Is Renesas U2A16 and other Renesas Microcontrollers included?

ere any case of 100BASE SGMII being used in Renesas microcontrollers?

(3) Loop back

　IF xMII loopback (SGMII) is NG, Is it mean that Renesas microcontrollers are not supported?

　Does xMII Loopback go through 8B10B encoding and decoding, or without encoding and decoding?

Regards,

Norio.

Hi Melissa,

I'm sorry for the time.

I find TDA4 processor's errata.

J721E DRA829/TDA4VM Processors Silicon Revision 1.1/1.0 (Rev. D) (ti.com)

P76 i2362

(1)How about DP83TC812S-Q1 ?　Is  it behave the same?

(2) I fined two pattern at DP83TC812S-Q1

　　Case1     sop x1 Preamble x 69  sfd  x10 　(Payload )　eop2 x1

　　Case2     sop x1 Preamble x 68   sfd x 10　(Payload)　 eop2 x2

　　Are there any other patterns that can occur?　Please tell us all the patterns.

　　I think it is necessary to check whether the MAC （RH850）side supports it.

Regards,

Norio.

Hi Norio,

Norio Hasegawa said:

(1) Did you find anything out of the materials?

　Other users have also encountered 100BAE SGMII NG, so I don't think it's a problem with the circuit or pattern.

　Is there any way to investigate the problem? Can you give me some more advice?　

We are analyzing the 8b/10b encoding data you provided. Do you also have a scope shot of the eye, similar to the one below?

Norio Hasegawa said:

(2) Renesas Microcontrollers 

＞The DP83TC812 should support any MCU that implements SGMII correctly

　Is Renesas U2A16 and other Renesas Microcontrollers included?

　

ere any case of 100BASE SGMII being used in Renesas microcontrollers?

You may need to check with Renesas on their support for 100Mbps SGMII. The 812  has been selling for a years and many customers have used SGMII in the past without issue. This may be a issue unique to the RH850 in connection with our 812. 

Norio Hasegawa said:

(1)How about DP83TC812S-Q1 ?　Is  it behave the same?

I will check with our internal team.

Norio Hasegawa said:

(2) I fined two pattern at DP83TC812S-Q1

　　Case1     sop x1 Preamble x 69  sfd  x10 　(Payload )　eop2 x1

　　Case2     sop x1 Preamble x 68   sfd x 10　(Payload)　 eop2 x2

　　Are there any other patterns that can occur?　Please tell us all the patterns.

　　I think it is necessary to check whether the MAC （RH850）side supports it.

This behavior is not expected. Is there a way for you to measure the PHY's SGMII output before and after disconnecting it from the Renesas MCU?

Best regards,

Melissa

Hi Melissa,

Thank you for contacting.

Sorry,  Currently, we cann't prepare an oscilloscope that can decode 8B10B and wide bandwidth.

　I did not check the waveform of the SGMII connection sequence at CPU startup.

　Please let me know if there is a document that describes the SGMII disconnecting /start up sequence.  

    Are there any sequences in the sequence that might affect Nibble shift?

Regards,

Norio.

Hi Norio,

Were the previous scope shots taken at 3rd party then?

You can refer to the SGMII spec: https://ia803002.us.archive.org/25/items/sgmii/SGMII.pdf

Best regards,

Melissa

Hi Melissa,

・The previous data was obtained by a Oscilloscope Vendor for the purpose of investigating this phenomenon.

・The reference documentation doesn't mention the startup sequence, only Auto-negotiation.

       In the PHY register check, Auto-negotiation is complete.

I heard from Open Alliance,  SGMII specification is based on Cisco's specifications, but there is some missing information.

Therefore, it is necessary to check the interoperability between the PHY and the MAC.

I would like to know TI's SGMII all packet pattern  at 100BASE mode.  And check with Renesas.

Regards,

Norio.

Hello Norio, 

Melissa is currently out of office and will reply upon return.

Regards,

Avtar

Hi Norio,

This discussion has been ongoing over email, let's continue the conversion there as it is getting difficult for me to keep up with email and E2E at the same time. Locking this thread now. 

Best regards,

Melissa