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DS110DF111: CDR Not Locked using 10GBASE-ZR SFP+ Transceivers

Jack Zhang
Intellectual 480 points
Part Number: DS110DF111

Hello,

I have a custom a PCB design that involves the DS110DF111 to interface between a processor to Cisco optical switch. I'm currently testing with Cisco Compatible Duplex 10GBASE-ZR/ZW Ethernet 10G Ethernet / 8G FC SFP+ transceivers designed for long distance optical communications up to 80 km with signaling rates up to 10.3125 Gbps, which are connected via optical patch cables between custom PCB SFP+ ports to the SFP+ ports on the switch. Currently, the CDR is not locked on both CHA and CHB and no link is established. I would like to know if the DS110DF111 supports 10GBASE-ZR and what other retimer settings I could try to help establish a link. Please see attached device status screenshots from the SigCon Architect GUI and the register .cfg file if this helps. Also attached is a snippet of the schematic for the PCB design using the retimer. Thank you in advance for any help that can be provided!

ds110df111.cfg

  • 0
    TI__Mastermind 19640 points

    Hi Jack,

    I expect DS110DF111 to support typical 10GBASE-ZR applications. I reviewed your register dump and I have a few initial questions/debug ideas.

    1. What is the measure of insertion loss on the receiver of each retimer channel?
    2. I see ch A is configured for 10 GbE and 1 GbE through default register settings. I see ch B is also configured for 10 GbE and 1 GbE via manual data rate configuration (registers 0x60-0x64). I suggest configuring both channel data rates via default settings for consistency.
    3. I see the driver polarity is inverted on both channels (0x1F=0xD5). Can you confirm your layout matches this register setting?
    4. I see 0x24=0x40 on both channels, enabling No Lock on DFE error. This setting may be preventing the channels from obtaining CDR lock. Can you try disabling this setting (0x24=0x00)? Please perform a CDR reset after writing this register setting to run adaptation again (write 0x0A=0x1C, then write 0x0A=0x10).
    5. I see you are using adapt mode 2 on both channels: adapt CTLE until optimal, then DFE, then CTLE again (0x31=0x40). Can you try using adapt modes 1 and 3 as well (0x31=0x20, 0x31=0x60)? Please perform a CDR reset after writing this register setting to run adaptation again (write 0x0A=0x1C, then write 0x0A=0x10).
    6. If possible, can you try transmitting a PRBS31 pattern on the link instead of normal traffic? I'd like to see if the retimer channels can obtain lock to a PRBS pattern. This would indicate the no lock issue is pattern dependent.

    Best,

    Lucas