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DS32ELX0421: Line Rate / Pattern Requirement when DC Balancing and Remote Sensing are off

Joachim Mueller
Prodigy 25 points
Part Number: DS32ELX0421
Other Parts Discussed in Thread: DS32ELX0124,

We are testing a loopback DS32ELX0124 to DS32ELX0421 where DC Balancing and Reomte Sensing are not used.

The datasheet specifies CML Line Rate of 1.25 to 3.125Gbps with an alternating pattern 1-0 pattern. This is an ideal pattern but unusual.

What is the minimum required transitions (in total and per 10 Bits) for a reliable PLL lock at the receiver side?

Do you have a recommendation for a power-up sequence?

  • 0
    TI__Genius 14335 points

    Hi Joachim,

    Which signal are you referring to about the minimum transitions? Is it TxCLKIN? The requirements for the input DDR clock are in the "LVDS Timing Specifications" section.

    I will check whether we have power-up sequence recommendations and get back to you.

    Best regards,
    Ikram