• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 596 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83869HM: Abnormal analog supply voltage(VDDA2P5)

Nam, Dino
Expert 6445 points

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Tool/software:

Dear team, 

There is issue on customer board. The customer use DP83869 device on both board. 

First board power on, DP83869 is Forced 100M mode, but we can see abnormal voltage other side board(second board). Although we don't supply any power at second board but we can see about 400mV voltage on VDDA2P5 line and 50mV on VDDIO line. Is this phenomenon normal situation? Please let me know your opinion. 

It is critical issue. please let me know your opinion as soon as possible. 

Thank you.  

  • 0
    TI__Mastermind 25378 points

    Hi,

    This behavior is documented for DP83869, please refer to this FAQ:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1396478/faq-dp83867e-expected-back-powering-on-power-supply-pins

    From the PHY-side, no functional issues are expected with this voltage on the rails before powering.

    However, if there are other components on the board that rely on VDDA2P5, I recommend confirming they will not be damaged by this 400mV.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    TI__Expert 6445 points

    Hello Evan, 

    Thank you for your comment. More questions. 

    1. Could you share internal block diagram including power path to recognize "the MDI side can back power the VDDA_2P5 pin."?

    2. If the customer set Auto-negotiation mode, Is there no issue like "The MDI side can back power the VDDA_2P5 pin."?

    3. We can see 50mV on VDDIO line also. Is this phenomenon also normal operation? 

    4. When below set up(red box and comment) => In forced mode, Board A will begin transmitting data to B board =>  Is there possibility that the VDDA_2P5 pin of Board B is 2.5V(original power supply + 0.8V(from the MDI pins of the DP8386x PHY)? 

      - Board A is powered on and configured into a forced speed mode (Auto-negotiation disabled)

      - Board B powered on and configured into Auto-negotiation mode 

    Thank you. 

  • 0 in reply to Nam, Dino
    TI__Mastermind 25378 points

    Hi Nam, Dino,

    1) This cannot be shared unfortunately.

    2) In the case with one board powered off, the MDI is not expected to back power VDDA_2P5 while auto-negotiation is enabled. The reason for this is that MDI signaling will be inactive if only one PHY is alive with auto-negotiation enabled. Forcing speeds with auto-neg disabled will allow MDI signaling regardless of link partner status.

    3) This 50mV is not a concern.

    4) I will check and confirm.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    TI__Expert 6445 points

    HI Evan, 

    Thank you for your strong support. 

    For internal block, we have to explain this issue to the customer. Even if it's simple, please share a block including power path to explain Back-Powering on Power supply Pins. 

    I understand this back powering will not damage the DP8386x PHY and will not result in any functional issues. But due to the potential 0.8V back-powering voltage, The PMIC on customer schematic does not turn on at all. The PMIC has function to check residual voltage before the power-up sequence. It is critical issue on customer side. please review it again and let me know your opinion. 

    Evan Mayhew said:
    4) I will check and confirm.

    When can I get your feedback?   Please let me know approximate schedule. 

    Thank you. 

  • 0 in reply to Nam, Dino
    TI__Mastermind 25378 points

    Hi Nam, Dino,

    I cannot share details publicly for this.

    Can the schematic be shared so I can review power scheme for possible workarounds? (can email at e-mayhew@ti.com)

    Regarding (4), I have confirmed that this is not a concern when the PHY is powered. The VDDA2P5 rail will not be back-powered past 2.5V, regardless of MDI activity.

    Thank you,

    Evan