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DP83848K: Reset versus Clock in RMII mode

Inge Johansen
Prodigy 10 points
Part Number: DP83848K

Tool/software:

The PHY DP83848K is connected to a MAC in the imx.93 CPU. The interface is set up for RMII operation.

The i.mx93 provides the 50 MHz clock and is connected to the X1 pin of the PHY.

The 50 MHz RMII clock starts running after release of the RESET_N signal of the PHY.

Must the 50 MHz RMII be running during  the RESET_N low period?

In our application it seem to function (RESET_N negates prior to RMII clock),

However the datasheet indicates that RMII_CLK  must be running during RESET_N active.

Could you please clarify.

  • 0
    TI__Mastermind 18262 points

    Hi Inge,

    Inge Johansen said:
    Must the 50 MHz RMII be running during  the RESET_N low period?

    Yes, X1 clock input is required during reset and power sequence to ensure the PHY initializes properly.

    How is the i.mx93 50M clock output tied to RESET_N signal? Can the timing be changed on the firmware side for clock to be available during PHY RESET_N low?

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 10 points

    Thank you for fast response. The 50 MHz RMII clock is not tied to RESET_N of the PHY.

    On our prototype board the global powerup RESET_N is Resetting the i.mx93 CPU and the DP83848 at the same time. When RESET_N is negated the i.mx93 starts setting up the RMII and the 50 MHz RMII clock output. 

    As mentioned, this RESET_N sequence do function on our prototype board. PHY starts running correctly.

    Anyway, on the next rev of the board, we will use a separate GPIO from the i.mx93 to control the RESET_N input of the DP83848.

    Best regards

    Inge

  • 0 in reply to Inge Johansen
    TI__Mastermind 18262 points

    Hi Inge,

    Thanks for clarifying.

    Can you please share a capture of the current working RESET_N sequence?

    I'd like to confirm the delay between RESET_N ramp and XI on the PHY-side.

    Best regards,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 10 points

    Hi Evan,

    I did a measurement on our prototype.

    The Reset sequence on our prototype board starts with RESET_N low to the DP83848K (no RMII clocks)

    Then RESET_N is negated (set high). After 2.5 Seconds the RMII_CLK from the i.mx93 starts running.

    As mentioned in my previous mail, the DP83848 starts operating on our prototype after the RMII_CLK is applied.

    By the way, the evaluation board DP83848K-MAU-EK, The RESET_N pin is unconnected:

     https://www.ti.com/lit/df/snlr011a/snlr011a.pdf?ts=1725454539560

    Could it be that the PHY is reset via the MDC/MDIO interface?

    Best regards

    Inge

  • 0 in reply to Inge Johansen
    TI__Mastermind 18262 points

    Hi Inge,

    Although the 2.5 second delay is working for your prototype, this may lead to corner cases where PHY is locked up during initialization.

    We recommend having XI available at the time of reset.

    For DP83848K-MAU-EK, you are correct that PHY is reset using MDC/MDIO. I recommend having option for RESET_N pin to reset, to avoid dependency on register access for reset.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 10 points

    Hi Evan,

    I also see that the DP83848 also includes an internal power-on reset (POR) function. see 6.4.6.

    The Hardware Reset (6.4.6.1) should be better described. As I understand,  during the HW reset the X1 clock must be running.  

    From datasheet:

    6.4.6 Reset Operation
    The DP83848x includes an internal power-on reset (POR) function and does not need to be explicitly reset
    for normal operation after power up. If required during normal operation, the device can be reset by a
    hardware or software reset.


    6.4.6.1 Hardware Reset
    A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 μs, to
    the RESET_N. This will reset the device such that all registers will be reinitialized to default values and the
    hardware configuration values will be re-latched into the device (similar to the power-up/reset operation).

    Best regards

    Inge Johansen