Tool/software:
The PHY DP83848K is connected to a MAC in the imx.93 CPU. The interface is set up for RMII operation.
The i.mx93 provides the 50 MHz clock and is connected to the X1 pin of the PHY.
The 50 MHz RMII clock starts running after release of the RESET_N signal of the PHY.
Must the 50 MHz RMII be running during the RESET_N low period?
In our application it seem to function (RESET_N negates prior to RMII clock),
However the datasheet indicates that RMII_CLK must be running during RESET_N active.
Could you please clarify.