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SN65DP159: SN65DP159RSBT

Malsekar Karthik Krishna
Prodigy 120 points
Part Number: SN65DP159

Tool/software:

Hi Team,

1. If i give enough time for OE to be de-asserted until which all the VCC and VDD are stable, is there still a requirement of 'td1' to be taken into consideration since there will be a delay of 1.4ms between VCC and VDD in my design?
2. What is maximum acceptable time for OE to be kept de-asserted? ( I am using RC filter for delay)
3. Also, is the delay of 1.4ms between them acceptable? 
4. Also can the stability of VCC before VDD or vice versa can be ignored?

Image attached below:



Thanks,
M Karthik

  • +1
    TI__Mastermind 24000 points

    Hi M Karthik,

    1. If you adhere to td2 then it is ok to disregard td1

    2. You can keep OE de-asserted (low) for as long as needed. The main requirement is that both VCC and VDD are stable before OE is asserted.

    3. Yes you can have a 1.4ms delay between VDD/VCC becoming stable

    4. Yes you can ignore the stability of VCC relative to VDD (or vice-versa) if OE is held low until both are stable.

    Best,

    Shane