DP83822I: The output issue for DP83826I

Hi Liang,

If possible, may I ask what is clock signal input to XI pin? Is it 25MHz or 50MHz.

A schematic would be helpful for us to debug.

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Regards,

Hillman Lin

Hi Hillman,

Please refer to below schematic:

Hi Hillman,

We use the RMII mode based on 50MHz, and now, the failure IC is auto set to RGMII mode, we force to RMII mode that the issue is solved,

we have no idea what this issue happen, we original design is based on the MAC interface configuration in datasheet, thanks.

Hi Liang,

If possible, could you probe RX_ER and RX_DV when the PHY is power up to confirm on the strap stage. I was thinking the MAC impedance or outputting some signal the PHY is power up

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Regards,

Hillman Lin

Hi Hillman,

Plesae refer to below waveform for RX_ER and RX_DV VS RESET:

Hi Liang,

Based on the scope capture, it seems like the RX_ER always have a voltage when you are resetting which is the test mode 2 based on the strap table.

Is the scope capture during the power up stage? Could you also add AVDD voltage rail in the capture?

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Thank you,

Hillman Lin