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SN75HVD11: How to understand VIT+、VIT-、Vhys

J-ZHOU8
Expert 3010 points

Part Number: SN75HVD11

Tool/software:

Hello experts

Hope this finds you well.

How to understand VIT+、VIT-、Vhys in datasheet please?

Please tell us what voltage the TTL level output (R in the following figure) changes after receiving with the Receiver. Specifically, what is the voltage of the differential input signal (a and B in the following figure)?

Regards,

Jieyu Zhou

  • 0
    Guru 322000 points

    This is explained in table 9-2.

    The hysteresis ensures that small noise does not make the receiver switch again, i.e., after the receiver has switched, the voltage must go more than 35 mV in the other direction for the receiver to switch back,

  • 0
    TI__Guru* 79291 points

    I'm going to use SN75HVD11 for all examples below:

    J-ZHOU8 said:
    How to understand VIT+

    If A-B voltage is above -0.01V (max VIT+), then R will be a logic high.

    J-ZHOU8 said:
    VIT-

    If A-B voltage is below -0.2V (VIT- min) then R will be a logic low.

    J-ZHOU8 said:
    Vhys

    There is a 35mV difference typically between VIT+ and VIT-. So if VIT+ is actually -0.065 and VIT- is actually -0.1V then the total difference is 35mV. The min and max values are just what we guarantee, VIT+ and VIT- at usually not the max/min values.

    J-ZHOU8 said:

    Please tell us what voltage the TTL level output (R in the following figure) changes after receiving with the Receiver. Specifically, what is the voltage of the differential input signal (a and B in the following figure)?

    So if A-B voltage goes to -1.01V then goes back to -0.7V then goes back to -1.01V R will remain low. (We assume VIT- is actually -1V in this example).

    If A-V voltage goes from -1.01V to -0.05V then back to -1.01V then R might go high temporarily before going back low because it crossed over -0.065V. 

    Logic high refers to 3.3V and logic low refers to GND in all my examples and assumes Vcc is 3.3V

    -Bobby

  • 0 in reply to BOBBY
    TI__Expert 3010 points

    Hello Bobby, Hello Clemens

    Thank you so much for your reply.

    Customer try to plot and would you please confirm if this understanding is correct or not?

    If this is not correct, please let us know where is wrong.

    If the time on the horizontal axis t passes, is it correct to assume that the R output does not change within the range of H (within the range of Hysterisis)?
    Also, within the range of D, does it become L and then L=> H?
    (If the a-B voltage on the punch picture rises, does it also change to H and then to H=> L?)

    Regards,

    Jieyu

  • 0 in reply to J-ZHOU8
    Guru 322000 points

    The plot is correct for some typical values.
    When the current output state is high, then the differential input voltage must go below −0.1 V for the output to switch to low.
    When the current output state is low, then the differential input voltage must go above −0.065 V for the output to switch to high.
    In the D ranges, nothing happens.

    The typical values are not guaranteed. The actual switching levels (left and right of the H range) can be anywhere between −0.01 V and −0.2 V, and the hysteresis can be different from 0.035 V.

  • 0 in reply to J-ZHOU8
    TI__Guru* 79291 points

    Clemen's comments are correct but I'll add my own to provide my thought as well.

    J-ZHOU8 said:
    If the time on the horizontal axis t passes, is it correct to assume that the R output does not change within the range of H (within the range of Hysterisis)?

    Yes this part is true.

    J-ZHOU8 said:
    Also, within the range of D, does it become L and then L=> H?

    This part is a maybe. The prop delay for the HVD11 is 40ns. If the edge is very fast it might you might drop below -0.2V and it would be outside the D window. If the edge is slower than 40ns, it probably will happen in the D window. 

    J-ZHOU8 said:
    (If the a-B voltage on the punch picture rises, does it also change to H and then to H=> L?)

    If it enters the H window but does not completely pass through the H window then it should not change R output. In the low to high to low example, if it goes to -0.1V then goes up but doesn't pass the -0.165V then goes back down typically it won't change the R output. This uses the typical hysteresis number. If the Hysteresis was smaller then it's possible (may still not occur though).

    -Bobby

  • 0 in reply to BOBBY
    Expert 2865 points

    Hi Bobby, Hi Clemens,

    I am taking over this issue and dealing with it. Thank you and best regards,

    If the threshold is -0.01 V, will the R output be H/L even if inputs A and B are not reversed?

    If the voltages of A and B are the same, the R output will be High because the threshold is negative.

    Does this conflict with the last line on page 17 of the data sheet as below?

    ''When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,''

    Let me check just in case.

    Best Regards,

    Ryusuke

  • 0 in reply to R.Fukunaga
    Guru 322000 points

    That description is wrong; it was copied from an older device that had a positive VIT+. With the SN75HVD11, the threshold was made negative to ensure that an idle bus with VID = 0 results in a high output.

  • 0 in reply to R.Fukunaga
    TI__Guru* 79291 points

    Clemens is correct.

    If your A-B voltage were -0.01V, I would expect the R pin to remain high since the Vhys is 35mV. 

    -Bobby