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TMDS171: TMDS171I

Roberto Teodori
Prodigy 20 points
Part Number: TMDS171


Tool/software:

Hello,

my name is Roberto Teodori and I need a clarification about one of the features listed in the TMDS171/I Datasheet.

I' m referring to Inter-Pair Skew Compensation of 5+ Bits.

5+ Bits means that skew compensation works for more than 5 Bits, for example can compensate up to 10 bits?

Thank you for your support

Best Regards

Roberto Teodori

  • 0
    TI__Guru**** 180881 points

    Roberto

    Your understanding is correct, but the max input inter-pair skew tolerance is 1.8ns.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Thany You for your answer.
    Sorry, but I have to admit that I did not understand very well what you meant.
    I would like to give you an example: if the skew compensation can be greater than 5bit (5+), as specified in the TMDS171 datasheet, with a bit rate per channel of 1Gbit/s I get a 5bit time equal to 5ns which is much greater than 1.8ns.
    Could you help me understand better how the skew compensation of the TMDS171 works?
    Thank you so much for your patience.
    Best Regards
    Roberto Teodori

  • 0 in reply to Roberto Teodori
    TI__Guru**** 180881 points

    Roberto

    There is actually a typo in the datasheet on the inter-pair skew and needs to be corrected. The inter-pair skew in the datasheet should read:  T_RX_INTER (MAX) : 0.2*Tcharacter +1.78 ns. The TMDS171 datasheet was geared towards HDMI 1.4B devices and thus the value in the HDMI1.4b spec is being used.

    The TMDS171 also supports both re-driver and re-timer mode and skew compensation is only provided in the re-timer mode. TMDS171 is in re-timer mode when data rate is between 1.2G and 3.4G. So for the 1Gbps example above, TMDS171 will be be in re-driver without any skew compensation. 

    But for data rate of 3.4Gbps, the TMDS171 will be in re-timer mode and provides 2.37ns input skew compensation.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Thank you David for your answer.

    Actually I forced the TMDS171 in retimer mode via I2C bus even if the bit rate is lower than the minimum specified to automatically switch to retimer mode.

    As we have a skew issue between DVI lines equal to 10 bits at 1Gbit/s bit rate per channel I verified the compensation is working well aligning the output stream as shown in the figures below.

    Below is the input DVI stream of TMDS171 with one channel shifted of 10 bits:

    Below is the output  DVI Stream of TMDS171 with the skew corrected.

    Seems the retimer can compensate much better than specified in the datasheet. 

    I would like to find a rational explanation to understand if the possible implementation of the TMDS171 in our project represents a valid cure for the problem without the need to redesign the entire board.

    Thank you for precious support

    Best regards 

    Roberto Teodori

  • 0 in reply to Roberto Teodori
    TI__Guru**** 180881 points

    Roberto 

    If you read bit 7 of register 0x15, are you seeing this bit being set to 1? When the TMDS171 is in the retimer mode, it will de-skew the inter-pair skew between the input data lanes. The DESKEW_CMPLT bit will be set to 1 when the TMDS171 completes the de-skew process.

    Judging from the scope waveform, it does appear that TMDS171 is correctly performing its de-skew function in re-timer mode. Reading the above bit will further confirm this. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Thank you very much for precious help.

    Best regards

    Roberto