Part Number: DP83826I
Tool/software:
Hello,
The maximum low level output voltage is listed as 0.8 V. Is this correct? I would expect a lower value like 0.4 V for a standard 3.3 V LVTTL/LVCMOS driver.
There is no margin for error between VOL and the VIL of the receiver if VOL = 0.8 V.
Typical 3.3 V LVTTL/LVCMOS levels from SCEA021A.
Hi Kristjan,
Looking into the VOL_3v3 spec, the 0.8V VOL maximum seems to be coming from a relatively high load current of 8mA. You can see this in the DP83826 datasheet Figure 9-5:
An example where a high load current could be an issue is if you are connecting an output directly to the 3.3V VDDIO rail and attempting to drive low. This would cause the output to sink large amounts of current and raise the VOL spec similar to the datasheet figure. You could think of this as the output fighting to drive the voltage rail low, but not having enough drive strength to do so.
If you are strapping the PHY correctly (current limiting resistors on LEDs, appropriate PU/PD resistors on strap pins) the PHY's output pins should not sink enough current to reach a 0.8V VOL. Using strap settings as an example, with the recommended 2.49k pullup to 3.3V VDDIO, the current sink into a connected output would be (at most) 3.3/2490 = 1.3mA. Looking at figure 9-5 from the DP83826 datasheet, we would expect VOL to stay under 0.2V in this case.
What I'm investigating now is why we've got 0.8V as the max VOL_3V3 with a test condition of 2mA load. According to figure 9-5 the max should be closer to 0.2V at a 2mA load current.
I will look to update this thread with any more findings, but I hope this helps to explain your original 0.8V spec question. Let me know if you have any other questions.
Best,
Shane
Thanks Shane! That does alleviate my initial concern.
Does Figure 9-5 account for the integrated MAC series termination resistance? If so, is it with fast mode or slow mode? I saw in another forum post that the 50 Ω spec in the datasheet is for fast mode and slow mode is 90 Ω.
Hi Kristjan,
Figure 9-5 shows the output sink-current relationship to VOL, and would be applicable to either fast or slow mode.
Fast/Slow mode changes the internal termination resistance on the MAC interface. This will change the amount of current flowing into the output when driving low, but would not change the current-to-VOL relationship shown in Figure 9-5.
In both fast/slow mode cases, if the PHY is strapped correctly you should not be reaching 8mA of sink current (0.8V VOL). In a real application, the output will route to a connected receiver and a VDDIO voltage rail through the 2.49k strapping resistor. The receiver will not contribute current, so the only source of current for the PHY to sink would be through the 2.49k resistor. I drew a diagram to help show this:
Best,
Shane
