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DP83867IR: Shutdown Sequence

Kato Yuya
Prodigy 50 points
Part Number: DP83867IR


Tool/software:

Hi

I'm using a PHY [DP83867IRRGZT] on a board I designed, but during shutdown sequence checks it is behaving differently than expected, violating the FPGA shutdown sequence, so I'm looking for a way to improve this.

After powering on the system and establishing Ethernet communication, when powering off the system, the 2.5V voltage supplied to the PHY remains at 500mV for approximately 750ms, then discharges to 0mV over 100ms.

If Ethernet communication is not established, the voltage does not remain at 500mV, and immediately discharges to 0mV.

The PHY is operating with a dual power supply configuration (1.0V, 2.5V) and the VDDIO-Supply supplies 1.8V.
The MODE design is as follows:

RX_D0: PHY_ADD0,1 ⇒ MODE1
RX_D1: PHY_ADD2,3 ⇒ MODE1
RX_CTRL: Autoneg ⇒ MODE3
LED_2: RGMII Clock Skew Tx[0],[1] ⇒ MODE1
LED_1: ANEG_SEL, RGMII Clock Skew Tx[2] ⇒ MODE1
LED_0: MirrorEnable ⇒ MODE1
GPIO_0: RGMII Clock Skew[0] ⇒ MODE1
GPIO_1: RGMII Clock Skew[1,2] ⇒ MODE1

I will post the captured waveform.

Is this a characteristic of the PHY?
Or can it be resolved by adjusting the OHY settings?
Please let me know.

Best Regard,Kato

  • 0
    TI__Genius 15266 points

    Hi Kato-san,

    This is not the characteristic of the PHY.

    Could you provide more information on how the other power supplies to the PHY are turned off?

    In addition, are the power rails shared by other devices?

    Lastly, it would be great if you could share the schematic so we can check to see if there are any components that may be charged causing such a long dissipation.

    I will friend request you so please feel free to share the wchematic via private message.

    Best,

    J

  • 0 in reply to J
    TI__Genius 15266 points

    Hi Kato-san, 

    I just measured this in our EVM and this is an expected behavior of the PHY when there is MDI link and the 2.5V goes down. 

    This will not damage the PHY and is an expected behavior of the PHY. 

    Best,
    J

  • 0 in reply to J
    Prodigy 50 points

    Hi J,

    Sorry for the late reply.
    I will see if I can provide a circuit diagram.

    So this is a characteristic of the PHY.
    I understand.
    Is there any way to improve this shutdown sequence?
    2.5V is used as the FPGA bank power supply voltage,
    which would significantly violate the FPGA shutdown sequence.

    Best Regard,Kato

  • 0 in reply to Kato Yuya
    TI__Genius 15266 points

    Hi Kato-san,

    Unfortunately, the MDI link is backpowerinh 2.5V so the only way to improve this would be to unplug the ethernet cable.

    Best,

    J