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TLK10232EVM: GENERAL PURPOSE (10G) SERDES MODE Ber Test

Part Number: TLK10232EVM
Other Parts Discussed in Thread: TLK10232

Using the original TLK10232EVM test board, some issues occurred. The mode used was 10G 1:1 at a rate of 4.9152.
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There are 4 test cases here: 
1. Using the A channel for testing, the electrical port of the optical module test board is connected to the tx of the bert, then connected through the optical fiber to the TLK10232EVM test board. Then, the rx of the bert is connected to the low-speed ls output port. The error rate tested out is at the level of 5*5e-6, which is very high.
2. Using the A channel for testing, the electrical port of the optical module test board is connected to the rx of the bert, then connected through the optical fiber to the TLK10232EVM test board. Then, the low-speed ls input port is connected to the tx of the bert. The error rate tested out is at the level of 5*5e-6, which is very high.
3. Using the B channel for testing, the tx of the bert is directly connected to the high-speed rx of tlk10232, and then the low-speed ls output port of tlk10232 is connected to the rx of the bert. The error rate tested out is at the level of 5*5e-6, which is very high.
4. Using the B channel for testing, the rx of the bert is directly connected to the high-speed tx of tlk10232, and then the low-speed ls input port of tlk10232 is connected to the tx of the bert. The error rate cannot be read and the connection to the bert fails. All the test configurations are the same. The principles of 2 and 4 should be the same. 2 can test, but 4 fails to test. This indicates that channel B itself has a fault. In fact, the error rate should not reach 5*5e-06 level in local testing.
Similarly, if modified to 10G: 1 to 2 mode, all the test cases cannot read the error rate from the bert and the connection to the bert fails.
I tried the suggestions on the forum:
(1):Write HS_ENTRACK (bit 15 of 0x1E.0004) with 1'B1, and write HS_EQPRE (bits 14:12 of 0x1E.0004) with 3'b101.
(2):Issue a data path reset by writing 1'b1 to bit 3 of 0x1E.000E.
The result is still the same.
Could you please check that area for any potential problems? Thank you.

  •        We use the method of generating test patterns externally with the help of BERT to test the GENERAL PURPOSE (10G) SERDES MODE(1:2 or 1:4). Is there anything wrong with this approach?

           Or are there any other recommended methods to verify that our configuration is correct?

          Thank you very much.