LSF0102: Schematic check

Hi Takumi-san,

Q1 : If MPU drives MDC signal using a push-pull output, then R0 is no needed and able to be removed. 

Q2 : 

• R1 : 10 kΩ is acceptable as an initial value, assuming: The MPU input leakage is low. The total trace/input capacitance is modest. And the MDIO waveform reaches a valid HIGH level before it is sampled. You could use something in the approximate 4.7-kΩ to 10-kΩ range. I would start with 10 kΩ, then verify the A-side rise time with an oscilloscope.
  
• R2 : 1.5 kΩ is a reasonable initial value, but its suitability depends on: MDC frequency; Total B1 capacitance; PCB trace length; DP83848 input capacitance;
  LSF and connector/parasitic capacitance
  The important limitation is that the MDC rising edge is generated primarily by the R2-Cbus RC network. At a high MDC rate, particularly near the DP83848 maximum of 25 MHz, the rising edge may be too slow. The DP83848 supports MDC up to 25 MHz, but it has no minimum frequency, so slowing MDC is allowed. What is MDC max frequency customer will use? 
  For initial testing, I recommend operating MDC at approximately 1–2.5 MHz, then checking both the 1.8-V and 3.3-V waveforms. Increase the MDC frequency only after confirming adequate rise-time and timing margin.
• R3 : The DP83848 datasheet explicitly states that its MDIO pin requires a 1.5-kΩ pull-up, which pulls the line HIGH during idle and turnaround periods. Make sure that 1.5 kΩ represents the total effective pull-up. Do not place several 1.5-kΩ pull-ups in parallel elsewhere on the MDIO bus.
• R4 : 200Kohm is correct.

Q3 : R5 is a series damping resistor, My recommendation: Provide a PCB footprint. Initially populate it with 0 Ω or possibly 22 Ω. Adjust based on oscilloscope measurements. However, its current location is not ideal. A source-series damping resistor should normally be placed close to the signal source. For MDC, the source is the MPU, not the DP83848. Putting 22 Ω between B1 and the DP83848 can still isolate the PHY input slightly, but it does not provide optimal source termination because the rising edge on B1 is generated by R2 rather than by a low-impedance 3.3-V driver. Place it close to the MPU side if the objective is MDC source damping.

Q4 : Do not route MDC and MDIO excessively long or near noisy Ethernet clock/data traces.

Thanks.

Brian