Dear all,
I´m Rainer from Hamilton Sundstrand Germany.
Some time ago, colleagues did a board for analog data acquisition with a DS90C241 24:1 LVDS serializer to output a continuous stream of measured values. In my current project I`m going to collect these data from up to 20 such sources and further process them within an FPGA. As there are not enough PLL sections available to recover all these asynchronuous data streams, the idea was to use SN65LVDS150 PLL building blocks to recover the LVDS clocks and feed them together with the LVDS datastreams into the FPGA. Does anybody has experience with this approach to tell me, whether it`s feasible? Or are there other solutions already prooven? The basic clock frequency of the DC90 chips on the data acquisition boards is 8MHz.
Thanks in advance for any input!
Regards, Rainer