Clocking and strobe polarity -- 65LVDS84

Hi Scott, regarding the SN75LVDS84:

1. In diagrams where CLKOUT is shown as a single-ended signal, it's representing the differential voltage.
2. You're correct; strobe polarity refers to the parallel side.
3. Yes, and the datasheet states "data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of
the input clock signal".

Thanks,
RE

Thank you for responding.  Can I assume that the differential voltage is computed as (CLKOUT+) - (CLKOUT-) ?

Scott

Yes.

As I dig deeper into the datasheet for the 65LVDS84, I see what appears to be an error.  The Switching Characteristics table on page 5 lists a set of delay times (td0, td1, etc.), which are defined as delays from CLKOUT's rising edge, and refer to Figure 6.  Figure 1 (page 6) is consist with the idea that the new cycle of data output starts after the rising edge of CLKOUT.  However, Figure 6 (on page 9) shows those times referenced to the falling edge of CLKOUT.  Is Figure 6 incorrect?

Thanks,

Scott

Hello Scott,

Your comment about Figure 6 seems to be correct, I will do a further investigation and let you know if the datasheet is updated.

Thanks.

Hi Scott,

First off, I believe you're referring to the SN75LVDS84A device.

According to Figure 1, a "new cycle" doesn't start on the falling nor rising edge of CLKOUT, but actually in the middle.  Each cycle has 2 bits when CLKOUT is high, 3 bits when CLKOUT is low, and 2 more bits when CLKOUT is high.  This is "Current Cycle" in Figure 1.

Figure 6 and td0/td1/td2/td3 describe the possible phase offset of bit positions versus the CLKOUT edge.  All the bits are +- 0.2ns of exactly 1/7th the clock period.  Figure 6 doesn't try to describe where a "new cycle" starts.

Thanks,
RE

Hi Ross,

I'm referring to the SN65LVDS84A; the 75LVDS84A is not automotive-qualified. 

I agree with your assessment of Figure 1, which is what confused me relative to Figure 6.  However, Figure 6 shows four data bits when CLKOUT is low and three when high, the opposite of Figure 1 and what you said above.

If Figure 6 is not trying to say when a new cycle starts, then it now makes sense as well.  I wish the new cycle start position was indicated in Figure 6 just to avoid confusion.

Please confirm if I'm reading this right:

1. Incoming parallel data is sampled on CLKIN falling.

2. That data starts appearing at the output shortly thereafter, midway through the high section of CLKOUT.

3. The first data bit to appear at the Y0 output after the falling edge of CLKOUT is D4?  Figure 1 is a little hard to read in that regard, plus there's my question about Figure 1 vs. Figure 6.

Thanks,

Scott

Hi Scott,

1. Yes.

2. I believe so.  There might not need to be too much concern over what the first LVDS bit is, and when it appears.  It will take multiple cycles for an LVDS receiver's PLL to lock, and for a display to align with the Vsync and Hsync frequencies.  It should all lock in a fraction of a second.

3. Yes, D4.

Hi Ross,

Thanks for your answers.  What do you think about my observation that Figure 6 shows four data bits when CLKOUT is low and three when high, the opposite of Figure 1?

I'm not so concerned about when the data first appears, but obviously the bit order is critical!

Scott

That appears to be an unintentional drawing scale error.  The industry standard for LVDS video and 7-bits/clock uses a CLKOUT high-level duty cycle of 4/7.  This doesn't impact any of the timings shown in Figure 6, but the CLKOUT rising edge should be shown at td3 instead of td4.  Sorry for the confusion.

Best regards,
RE

Hi Ross,

Thank you, I appreciate you clearing that up.  I'm realizing that we still have an unresolved question, though.  The timing table "SWITCHING CHARACTERISTICS" on page 5 of the datasheet gives the delays td0 through td6 as being from CLKOUT rising, but Figure 6 on page 9 shows them from CLKOUT falling.  Which is correct?

Thanks,
Scott

Congratulations, you've found another drawing error with Figure 6.  In this case, I think td0-td6 with respect to either edge has the same meaning.  All the bits start at 1/7th increments of the clock period, ±0.2ns.  I hope that's enough clarification; if not, let me know.

Thanks,
RE

Maybe I'm naive, but how can either edge have the same meaning?  Won't the receiver misinterpret the data if it's relative to the wrong clock edge?  If I set up the transmitter with the parallel data bits in a certain order, I need to be sure that the receiver is going to de-serialize them in the same order.  It seems to me that if the clock is 180 degrees out of phase vs. what I think it is, I'll have set up the data incorrectly and the LCD image will be faulty because D4 will be where D1 should be, etc.

Are we sure that the error is with Figure 6 and not with the spec table?

Thanks,

Scott

Yes, the clock's edge is absolutely important, regarding the sequence of serial bits in each lane.  Figure 1 describes this.  On Y0, D6 and D5 occur while CLKOUT is differential-high, and D4, D3, D2 occur while CLKOUT is differential-low.

When I said either edge has the same meaning for td0-td6, I'm referring to phase delay offsets.  Split the clock period into 7 edges.  2 of those 7 are real edges; think of the other 5 as pseudo-edges or bit-edges.  Data bit positions begin at each edge, ±0.2ns, regardless of which 2 of the real edges are rising versus falling.

Best regards,
RE

Ah, I see what you're saying: the data is synchronized to not just one but both edges, unlike a lot of synchronous systems, so while the spec table and Fig. 6 are inconsistent, they are both correct.  True?

Thanks,
Scott