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SN65LVCP418 device datasheet clarification

Jake Salmi
Expert 7055 points
Other Parts Discussed in Thread: SN65LVCP418

Hi folks - can you help with these  detailed questions below?

I have some questions regarding the SN65LVCP418 datasheet:

1. Table 1 Timing

 I2C Timing: On page 13, in Table 1 (I2C Timing), line 5 for the parameter tSU1, The Unit is identified as microseconds.

1a) Is 250 microseconds the correct value for the "Internal register setup time, SDA to SCL" for this device?

The I2C specification identifies "Data set-up time" as a minimum of 250 nanoseconds (ns).

1b) Also, in Table 1: Clock Low period of "I2C register" is 4.7 us minimum. Clock High period for "internal register" is 4 us minimum. Is there a difference between an "I2C register" and an "internal register".

1c) If so, what is the timing parameter for Clock LOW period for "internal registers" and what is the timing parameter for Clock HIGH period for I2C registers?

1d) Are the registers identified in Table 3 classified as "I2C registers" or "internal registers"?

2. I2C Addressing: On page 15, Table 2: The LSB for I2C devices is typically the "data direction bit" which identifies if a read or write operation is requested.

Table 2 appears to be misleading.

Would it be better to have Bit 0 identified as "X" with a note describing the data direction bit?

Also, it appears that the text "(addr2)" and "(addr1)" are not in the correct columns, and should be placed under "Bit 2" and "Bit 1", respectively.

3. Table 4: On Page 16, Table 4: Should Bit "2" (Port 3-State) be identified in the "Access" column as "R/W" rather than "R"?

4. Reserved Register: In the lab we have found that when we read "Output Port" registers (bits 7,6, and 5), We see the following: Output Port 0, bits 7 through 5 = "000" Output Port 1, bits 7 through 5 = "001" Output Port 2, bits 7 through 5 = "010" Output Port 3, bits 7 through 5 = "011"

  • 0
    TI__Mastermind 20820 points

    Hi Jake,

    1.  Table 1 Timing

    I2C Timing: On page 13, in Table 1 (I2C Timing), line 5 for the parameter tSU1, The Unit is identified as microseconds.

    1a) Is 250 microseconds the correct value for the "Internal register setup time, SDA to SCL" for this device?

    The I2C specification identifies "Data set-up time" as a minimum of 250 nanoseconds (ns).

                   The correct value should be 250ns per the I2C-Bus Spec V2.1 referenced on the datasheet. With a 100kHz (10us period) clock frequency the setup time would not be more than half the clock period.

    1b) Also, in Table 1: Clock Low period of "I2C register" is 4.7 us minimum. Clock High period for "internal register" is 4 us minimum. Is there a difference between an "I2C register" and an "internal register".

                   This is a typo, there is only registers.  

    1c) If so, what is the timing parameter for Clock LOW period for "internal registers" and what is the timing parameter for Clock HIGH period for I2C registers?

                   4us minimum, refer to answer b.

    1d) Are the registers identified in Table 3 classified as "I2C registers" or "internal registers"?

                   Refer to answer on b.

    2) I2C Addressing: On page 15, Table 2: The LSB for I2C devices is typically the "data direction bit" which identifies if a read or write operation is requested.

    Table 2 appears to be misleading, would it be better to have Bit 0 identified as "X" with a note describing the data direction bit? Also, it appears that the text "(addr2)" and "(addr1)" are not in the correct columns, and should be placed under "Bit 2" and "Bit 1", respectively.

                   Correct, text labels for “addr2” and “addr1” need to be shifted one column to the left and Bit 0 replaced with X or removed from the table.

    3) Table 4: On Page 16, Table 4: Should Bit "2" (Port 3-State) be identified in the "Access" column as "R/W" rather than "R"?

                    The datasheet was revised on November, 2011 and the revision history shows this was fixed at that time. Please download the latest datasheet from the Web.

    4) Reserved Register: In the lab we have found that when we read "Output Port" registers (bits 7,6, and 5), We see the following: Output Port 0, bits 7 through 5 = "000" Output Port 1, bits 7 through 5 = "001" Output Port 2, bits 7 through 5 = "010" Output Port 3, bits 7 through 5 = "011"

                    Your register reads for the output ports are correct.

    Regards,

    Mike