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Channel Link III

Bradley Helsel
Intellectual 260 points
Other Parts Discussed in Thread: DS92LX2121, DS92LX2122

Is it possible to configure the Channel Link III chipset DS92LX2121 and DS92LX2122 for a point-to-point interface and disable the back channel? I am trying to get a good eye diagram of just the LVDS transfer.

  • 0
    TI__Expert 7395 points

    Hi Bradley,

    The DS92LX2121/2 chipset is a bidirectional interface that uses Channel-Link III signaling; which transfers both high speed data and control data over the single diff pair. If you monitor the differential lines on the DIN/ROUT pins when the devices are connected together, you will observe mixing of both the forward and back channel signals (full duplex).  Hence, you will be unable to monitor the eye diagram. To measure the eye opening on Deserializer, there is a mode that provides a loop through output of the recovered forward channel (without back channel) after EQ equalization and prior to the CDR block. The loop through driver is available on RES pin 38 (CMLOUTP) and pin 39 (CMLOUTN). To enable the CMLOUT pins to measure the high speed eye opening, program register address 0x3F’h bit 4 to 0 (CMLOUT=enabled).

    Dac Tran

    SVA / APPS

  • 0 in reply to Dac Tran
    Intellectual 260 points

    Hi Dac,

    I will give that a try. Thank you for your response to my questions!

    Brad.

  • 0 in reply to Dac Tran
    Intellectual 260 points

    Hi Dac,

    I have another question for you.....

    Is it possible to damage the Serializer chip by tying the PDB pin directly to +3.3V? I was running in BIST mode and was using a clip lead between the +3.3V rail and PDB to enable the Serializer. After doing this several time, there was no Lock state and the Serializer would not go into BIST mode.

    Do the SCL and SDA line need to be pulled to VCC or GND during the BIST test? In my case they are floating when I am running the BIST test.

    Thanks.

    Brad.

  • 0 in reply to Bradley Helsel
    TI__Expert 7395 points

    Hi Brad,

    Tying the PDB pin directly to +3.3V should not damage the device. However, note the VDDIO and the control input pins must be at the same voltage levels (ie VDDIO = +3.3V). To enable the BIST function, make sure you are configured in the camera mode for Serializer (MS = 0) and Deserializer (MS =1). Also check the Deserializer GPIO[1:0] pins for the frequency source are set properly to table on page 30 of datasheet.  

    The I2C SCL and SDA lines can be left floating during the BIST test.

    Dac Tran

    SVA / APPS

  • 0 in reply to Dac Tran
    Intellectual 260 points

    Hi Dac,

    I have the system configured as you described. After running the BIST test for a while, the link begin to report more and more bit errors over time and loose lock. Eventually I could not get the chip set to communicate at all. The back channel was sending data but a Lock was never achieved and the BIST test would not start.  After some debugging I discovered that the PDB input on the Serializer had a direct short to the +1.8V plain (pins 14,15,18 and 34) through the Serializer chip. I have no explanation as to how this happened. I have since replaced this board with a function one and am continuing to validate the design.

    Thanks