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DS92LX2121 / DS92LX2122 CML transition time

Bradley Helsel
Intellectual 260 points

I was able to attain an Eye diagram from pins 38 and 39 of Deserializer and found that the CML low-to-high and high-to-low transition times are out of spec. The transition times in my system are just under 1nS.

1. Would there be any negative effects from this? (bit errors?)

2. The SER and DES are connected through a CAT5e cable, the standard cable used is 3m and changing to a very short cable (2 feet) does not have any effect on the transition time. What are my other options to increase the transition times of the diff pair?

Thanks.

Brad.

  • 0
    TI__Expert 7395 points

    Hi Bradley,

    The CML low-to-high transition times you referenced are specified for the DOUT+/- CML outputs on the Serializer side. The CMLOUT loop-through output driver (pins 38, 39) on Deserializer is not a characterized I/O. The intent of the loop-through driver is to monitor the eye diagram for the equalized signal.

    Dac Tran

    SVA / APPS

  • 0 in reply to Dac Tran
    Intellectual 260 points

    Hi Dac,

    Does this mean that the CMLOUT at pins 38 and 39 of the Deserializer are NOT representative of the signal quality of LVDS pair between the SER and DES?

    Can you give me a an explanation of the Receiver Input Equalization and how that effects RIN+/- at the DES?

    Thanks.

    Brad.

  • 0 in reply to Bradley Helsel
    TI__Expert 7395 points

    Hi Bradley,

    On the Deserializer, the signal between the equalizer and clock recovery portion is an internal node. The loop-through signal is fed into an output buffer driver on pins 38, 39. The CMLOUT differential signals will be representative of the recovered signals transmitted across the link.

    Dac Tran

    SVA / APPS