Hi,
I'm new in that forum and hopefully I'll be able to provide a detailed failure description.
Application: DS90CR215 - CHip is permanent enabled, TxCLK is also permanent applied and TXin_0-6 are in use.
The physical interface between the Tx & Rx chip is done via two connectors and a ~3m twisted pair cable. each for LVDS_DATA1 and LVDS_CLK.
The failure mode:
The bit stream feed in TXin_0 (at DS90CR215) should be identical to the decoded Bit stream available at RXout_0 (at DS90CR216) of course this is valid for all other input and output pins as well.
In my application, the Bit stream feed in TXin_0 is received at pin RXout_1; TXin_1 at RXout_2 ..... TXin_6 at RXout_0. So it seems to be that the decoding and mapping to the output pins is shifted by one. Consequently this drives my assumption that the skew between CLK and Data isn’t according spec. Due tot he complex application I’m pretty sure that the cable length for CLK & DATA isn’t 100% identical. How may I improve my physical interface to get this sorted out?
Any Idea, feedback highly appreciated.