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IBIS Model DS92LV2411 and DS92LV2412

Johann Amstutz
Prodigy 20 points
Other Parts Discussed in Thread: DS92LV2412, DS92LV2411, DS92LV2421, DS92LV2422

Hello

I've downloaded the IBIS Models of the serializer  DS92LV2411 and the deserializer DS92LV2412. We found out that the the serial input / output ports are not connected in the IBIS models.

Please send us a workaround to solve this problem! The serial input / outputs are the fastest interfaces and we are going to simulate the eye pattern!

 Port part of DS92LV2421:

19        DOUT-           NC

20        DOUT+           NC

 

Port part of DS92LV2422:

48        VDDIR           POWER

49        RIN+            NC

50        RIN-            NC

51        CMF             NC

52        ROUT+           NC

53        ROUT-           NC

54        VDDCMLO         POWER

Best Regards and thanks in advance

Johann Amstutz

  • 0
    TI__Genius 13475 points

    The IBIS models for this device only model the signal integrity of the input and output ports, not the behaviour of the device.

  • 0 in reply to Mark Sauerwald88474
    Prodigy 20 points

    This is exactly the point:  The eye pattern mentioned in my post shows the signal integrity (see the graphic below as an example). I'm not asking for a logical model of the device. Of course I would prefer the HSPICE model to calculate the signal integrity as we did in the past for more complex chips.

    The IBIS models 4760.DS92LV2411.ibs and 6064.DS92LV2412.ibs describe the signal behavior of the most input and output ports. But the serial ports are missing (see the part of the IBIS model I’ve copied). In both chips are the serial ports not connected and I’m going to ask you for an improved model

    [Pin] signal_name model_name R_pin L_pin C_pin
    1      DI22         I_DATA_SCR_HS50:  -> this port is connected to the description in the IBIS model
    19    DOUT-    NC                                   -> this port is not connected to the description in the IBIS model

     

    Best regards

    Johann Amstutz