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SN65LVDS314

Zhang Hong
Prodigy 20 points
Other Parts Discussed in Thread: SN65LVDS314

Hi,

I want to use 311 and 314 to connect a CMOS senser to FPGA. The RXEN is connected to VDD(1.8V),  LS1 -- VDD, LS0 -- GND, F/S  --GND,  SWAP  -- GND, CPOL -- GND.

When the CLK+/- input a paar of differential signal(offset 900mv, diff value about 300mvp-p) at 42Mhz, the output PCLK is 42Mhz but the voltage always about  2.7V with 42Mhz 500mVp-p, so we can't receive a stable CMOS/LVTTL period output.

What's wrong?

  • 0
    TI__Mastermind 20820 points

    Hi Zhang,

    I am moving this post to the appropriate forum that supports this part.

    Regards,

    Mike

  • 0
    TI__Mastermind 36085 points

    Hello Zhang,

        This seems to be a biasing issue, because the signaling level of the R[0:7], G[0:7], B[0:7], HS, VS, DE, and PCLK outputs of the SN65LVDS314 can be configured to be between 1.8 V and 3.3 V (nominal), depending on the voltage applied to the VDD_IO terminals. Therefore I suggest to check the voltage levels on the terminals VDD_IO and all the GND terminals.

    Also, You can send your schematics for a review to diego.cortes@ti.com

    Regards,

    Diego.

  • 0 in reply to Diego Cortes
    Prodigy 20 points

    Hi, Diego,

    Thanks for your help!

    We makde a low level mistake. The reason of the output with a DC is, the output signal was tied high by a MIPI converter. We plan to test 2 ways for receiving  the CMOS output MIPI/parallel interface, so we bind 2 kinds output signal together for the first version test board, these 2 kind chips shouldn't be welden on the same one PCB.

    And now 314 works correctly. It's easy to use.

    Thanks a lot!

    Zhang