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How to disable output of CLC001 driver?

Other Parts Discussed in Thread: CLC001, LMH0302, DS90CP22

I am researching a circuit to sense a single-ended signal and drive a differential 90-Ohm cable at 480Mbps, ground referenced. I discovered this nice device CLC001. I understand that it has current-source drivers set by Rref resitor to ground. What if I disconnect this resistor? I am thinking of using a open drain logic or a n-FET. Did anyone try to disable the current-source output of CLC001 this way? Thanks.

  • The CLC001 was not designed for this, but it would be feasible to disable the output in this manner.

    With the RREF resistor disconnected (RREF pin = floating), the supply current should be around 35 mA, and there will be no output.

    A better approach might be to use a more modern cable driver with an output disable function, such as the LMH0302.

    Gary Melchior

  • Thank you Gary for prompt response. I must completely misunderstood functionality of CLC001 circuit, and was confused with datasheet statement that "output of the CLC001 is a high impedance current source". I must falsely assume that with reference current at zero, the source current will be zero. Are you saying that with Rref floating both outputs will have 2.6V DC offset to ground (assuming 75 Ohms load resistors)? That would be terrible for my needs...

    Thanks.

  • The CLC001 has current source outputs.  When the RREF resistor is removed and the reference current is zero, the output current is indeed also zero.  The device supply current will drop from about 70 mA typical to 35 mA.  The outputs will both have zero DC offset (they will be at ground potential).

    Gary Melchior

  • Thank you very much! This is perfect for me. Power consumption is not my concern.

    One more question: if the differential input is zero (no signal), what would be the state of outputs? Does the circuit have the "fail-safe" input feature as the DS90LVxxx circuits have?

    Many thanks,

    -Ali

  • With no input, the CLC001 outputs (SDO+ and SDO-) will typically be in opposite states: one output in the high state (1.6V), and the other output in the low state (0V).

    The CLC001 does not include failsafe biasing.  If failsafe is needed, please refer to the following application note (AN-1194 Failsafe Biasing of LVDS Interfaces): http://www.ti.com/lit/an/snla051b/snla051b.pdf

    (The CLC001 incorporates an LVDS input stage very similar to the one used in LVDS devices such as the DS90CP22.)

    Gary Melchior