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TLK10022 configuration in 4:1 mode

manU li
Prodigy 80 points
Other Parts Discussed in Thread: TLK10022

Hello,
 I'd like to ask about configuration of TLK10022;
 
 1.My Application:
 The low speed side is connected to Aurora of Spartan-6 (4 lanes)
  1) mode 4:1;
  2) data rates of Low Speed is 2.5Gbps , High Speed is 10Gbps;
  3) reference clock 125M
  5) low  speed side: MPY = 10 , Rate scale = full (default);
  6) high speed side: MPY = 20 , Rate scale = full (default);
 
 2.My issue:
  1) Any lane of Aurora can't shake hands;
  2) TX and Rx of Aurora using K Characters handshake;
  3) Clkout pins output freq(Divide by 4):
   HS recovered byte clock = 156.25M
   HS transmit byte clock    = 156.25M
   HSRX VCO divide by 4   = 156.25M
   LS recovered byte clock = 62.5M
   LS transmit byte clock    = 62.5M
 
 3.My configuration:
  pins:
   PDTRXA_N   = high;
   REFCLK_SEL = low;
   PRBSEN     = low;
   
  <addr  =    data>
   0x1C  = 0x000C (bypass LS 8b/10b)
   0x1D  = 0x088C  (bypass HS 8b/10b)
   The other Registers : Default Value
  
  Read Status Data:
  <addr  =    data>
   0x0F  = 0x1803
   0x10  = 0xFFFD
   0x11  = 0x088C
   0x13  = 0x2944
   0x14  = 0x0000
  
   PS: When complete configuration , I read the state HS and LS of PLL, if locked, reset DATAPATH.
  
  
 4.My Question:
  Q1: HS transmit byte clock = recovered byte clock = 10G / Hs_Serdes / DIV = 10G / 20 / 4 = 125M
   Why I got 156.25M?
  Q2: In my application，what is the correct Read Status Data?
  Q3: Could you provide a configuration example to me? data sheet doesn't have it.
  
 Best Regards

  • 0
    TI__Intellectual 1485 points

    Hi,

    your calculations are right to answer Q1. But I need further details to figure out, why you get a different recovered output clock. Are you using one of our EVMs or your own setup?

    I set up a TLK10022-EVM in our lab with an external clock of 125 MHz, applied your settings and was able to get a recovered output clock of 125 MHz. So dependent on the situation my guess would be that the issue can be either in your setup or that you by accident use the EVMs internal clock, instead of an externally provided one.

    Regarding Q2: It depends on the applied settings. For example I read for Channel Status (0x0F) the value 0x1123.. The error counters then should be 0x0 ideally, if you loop back the LS_RX to LS_TX. I read for registers 0x13 different values, depends if synchronisation is achieved or not, or a FIFO overflow occurs. For register 0x14 I got the value 0x0004. Please keep in mind that I only set up a basic configuration with the values you provided me with and these values don't represent an optimal setting.

    Regarding Q3: I attached a general settings file, which is also available with the GUI of the EVM and initializes every register of the device.

    3678.TLK10022_General_Apply_Settings_Script.txt 
    //********************************************************************************************
//                                                                             
//                      Copyright Texas Instruments Inc                        
//                  TI Proprietary Information Internal Data                   
// This is a general provisioning script for the TLK10022 Apply Settings Portion of the GUI
//                                            
// Author:  Matt Sunna                                                  
// Modified Date:  July 12, 2013                               
// Revision: Rev 0.0                                                  
//********************************************************************************************


//********************************************************************************************
//                            Script Command Parameter Reference
//********************************************************************************************
//SET BOARD(BOARD_NUMBER)
//MDIO22 WRITE (CHANNEL_NAME,&REGISTERNAME)
//MDIO22 WRITE IMM (CH_ADDR,DEVICE_ADDR,REGISTER_ADDR,REGISTER_VALUE)
//MDIO22 READ (CHANNEL_NAME,&REGISTERNAME)
//MDIO22 READ UNTIL (CHANNEL_NAME,&REGISTERNAME,MASK,EXPECTED,TIMEOUT(ms))
//MDIO22 READ IMM(CH_ADDR,DEVICE_ADDR,REGISTER_ADDR,MASK,EXPECTED,TIMEOUT(ms))
//I2C WRITE (&REGISTER_NAME)
//I2C WRITE IMM (DEVICE_ADDRESS,REGISTER_ADDRESS, REGISTER_VALUE )
//I2C READ (&REGISTER_NAME)
//I2C READ UNTIL (&REGISTER_NAME, MASK, EXPECTED,TIMEOUT(ms))
//I2C READ IMM (DEVICE_ADDRESS,REGISTER_ADDRESS, MASK, EXPECTED,TIMEOUT(ms))
//DELAY			//This reads the test time per parameter field in the HS Link Optimizer and waits that amount of time
//WAIT(time ms)
//MDIO22 WRITE FUNC (CHANNEL_NAME, FIELD_NAME, Data[in hex])


//********************************************************************************************
//                            CDCM6208 Clock Generator Configuration
//********************************************************************************************
// Configure the Primary/Secondary Oscillator Enable Pins
I2C WRITE (REGISTER_04)
// Wait 100mS
WAIT(100)

// Disable the CDCM6208 during configuration
I2C WRITE FUNC (I2C_RESETN/PWR,0x0)
// Wait 100mS
WAIT(100)

//Configure the CDCM6208 Registers
SPI WRITE (CLK_REGISTER_0)
SPI WRITE (CLK_REGISTER_1)
SPI WRITE (CLK_REGISTER_2)
SPI WRITE (CLK_REGISTER_3)
SPI WRITE (CLK_REGISTER_4)
SPI WRITE (CLK_REGISTER_5)
SPI WRITE (CLK_REGISTER_6)
SPI WRITE (CLK_REGISTER_7)
SPI WRITE (CLK_REGISTER_8)
SPI WRITE (CLK_REGISTER_9)
SPI WRITE (CLK_REGISTER_10)
SPI WRITE (CLK_REGISTER_11)
SPI WRITE (CLK_REGISTER_12)
SPI WRITE (CLK_REGISTER_13)
SPI WRITE (CLK_REGISTER_14)
SPI WRITE (CLK_REGISTER_15)
SPI WRITE (CLK_REGISTER_16)
SPI WRITE (CLK_REGISTER_17)
SPI WRITE (CLK_REGISTER_18)
SPI WRITE (CLK_REGISTER_19)
SPI WRITE (CLK_REGISTER_20)
//SPI WRITE (CLK_REGISTER_21)
//SPI WRITE (CLK_REGISTER_40)

//Enable the CDCM6208 after the configuration is complete
I2C WRITE FUNC (I2C_RESETN/PWR,0x1)

//********************************************************************************************
//                            TLK10022 Soft Reset and Mode Configuration
//********************************************************************************************
// Configure MODE_SEL and ST Pins
I2C WRITE (REGISTER_05)

// Wait 100mS
WAIT(100)

// Soft Reset & disable global config
MDIO22 WRITE FUNC (GLOBAL,GLOBAL_RESET,0x1)
MDIO22 WRITE FUNC (GLOBAL,GLOBAL_RESET,0x0)
MDIO22 WRITE (GLOBAL,GLOBAL_CONTROL_1)

// Configure Operating Mode Registers
MDIO22 WRITE (A,CHANNEL_CONTROL_1)
MDIO22 WRITE (B,CHANNEL_CONTROL_1)

//********************************************************************************************
//                            CH A Provisioning
//********************************************************************************************

MDIO22 WRITE (A,CHANNEL_CONTROL_1)
MDIO22 WRITE FUNC (A,LT_ENABLE, 0x0)
MDIO22 WRITE (A,HS_SERDES_CONTROL_1)
MDIO22 WRITE (A,HS_SERDES_CONTROL_2)
MDIO22 WRITE (A,HS_SERDES_CONTROL_3)
MDIO22 WRITE (A,HS_SERDES_CONTROL_4)
MDIO22 WRITE (A,LS_SERDES_CONTROL_1)
MDIO22 WRITE (A,LN3_LS_SERDES_CONTROL_2)
MDIO22 WRITE (A,LN2_LS_SERDES_CONTROL_2)
MDIO22 WRITE (A,LN1_LS_SERDES_CONTROL_2)
MDIO22 WRITE (A,LN0_LS_SERDES_CONTROL_2)
MDIO22 WRITE (A,LN3_LS_SERDES_CONTROL_3)
MDIO22 WRITE (A,LN2_LS_SERDES_CONTROL_3)
MDIO22 WRITE (A,LN1_LS_SERDES_CONTROL_3)
MDIO22 WRITE (A,LN0_LS_SERDES_CONTROL_3)
MDIO22 WRITE (A,HS_OVERLAY_CONTROL)
MDIO22 WRITE (A,LN3_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (A,LN2_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (A,LN1_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (A,LN0_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (A,HS_TP_CONTROL)
MDIO22 WRITE (A,CLK_SEL_CONTROL)
MDIO22 WRITE (A,CLK_CONTROL)
MDIO22 WRITE (A,SKEW_CONFIG_CONTROL)
MDIO22 WRITE (A,HS_ALIGN_CODE_CONTROL)
MDIO22 WRITE (A,BIT_LM_CONTROL)
MDIO22 WRITE (A,LN3_LS_TXFIFO_CONTROL)
MDIO22 WRITE (A,LN2_LS_TXFIFO_CONTROL)
MDIO22 WRITE (A,LN1_LS_TXFIFO_CONTROL)
MDIO22 WRITE (A,LN0_LS_TXFIFO_CONTROL)
MDIO22 WRITE (A,LN3_LS_LOS_CONTROL)
MDIO22 WRITE (A,LN2_LS_LOS_CONTROL)
MDIO22 WRITE (A,LN1_LS_LOS_CONTROL)
MDIO22 WRITE (A,LN0_LS_LOS_CONTROL)
MDIO22 WRITE (A,LN3_DATA_SRC_CONTROL)
MDIO22 WRITE (A,LN2_DATA_SRC_CONTROL)
MDIO22 WRITE (A,LN1_DATA_SRC_CONTROL)
MDIO22 WRITE (A,LN0_DATA_SRC_CONTROL)
MDIO22 WRITE (A,LN3_LS_CH_CONTROL_1)
MDIO22 WRITE (A,LN2_LS_CH_CONTROL_1)
MDIO22 WRITE (A,LN1_LS_CH_CONTROL_1)
MDIO22 WRITE (A,LN0_LS_CH_CONTROL_1)
MDIO22 WRITE (A,HS_CH_CONTROL_1)
MDIO22 WRITE (A,VS_TX_MARKER_SEARCH_CHAR)
MDIO22 WRITE (A,VS_TX_MARKER_REPLACE_CHAR)
MDIO22 WRITE (A,VS_RX_MARKER_SEARCH_CHAR)
MDIO22 WRITE (A,VS_RX_MARKER_REPLACE_CHAR)
MDIO22 WRITE (A,VS_TX_IDLE_P_CHAR)
MDIO22 WRITE (A,VS_TX_IDLE_N_CHAR)
MDIO22 WRITE (A,VS_RX_IDLE_P_CHAR)
MDIO22 WRITE (A,VS_RX_IDLE_N_CHAR)

MDIO22 WRITE (A,VS_TX_SCR_CONTROL)
MDIO22 WRITE (A,VS_TX_SCR_SEED_CONTROL_1)
MDIO22 WRITE (A,VS_TX_SCR_SEED_CONTROL_0)
MDIO22 WRITE (A,VS_TX_SCR_POLY_CONTROL_1)
MDIO22 WRITE (A,VS_TX_SCR_POLY_CONTROL_0)
MDIO22 WRITE (A,VS_RX_DESCR_CONTROL)
MDIO22 WRITE (A,VS_RX_DESCR_SEED_CONTROL_1)
MDIO22 WRITE (A,VS_RX_DESCR_SEED_CONTROL_0)
MDIO22 WRITE (A,VS_RX_DESCR_POLY_CONTROL_1)
MDIO22 WRITE (A,VS_RX_DESCR_POLY_CONTROL_0)
MDIO22 WRITE (A,MC_AUTO_CONTROL)


//********************************************************************************************
//                            CH B Provisioning
//********************************************************************************************

MDIO22 WRITE (B,CHANNEL_CONTROL_1)
MDIO22 WRITE FUNC (B,LT_ENABLE, 0x0)
MDIO22 WRITE (B,HS_SERDES_CONTROL_1)
MDIO22 WRITE (B,HS_SERDES_CONTROL_2)
MDIO22 WRITE (B,HS_SERDES_CONTROL_3)
MDIO22 WRITE (B,HS_SERDES_CONTROL_4)
MDIO22 WRITE (B,LS_SERDES_CONTROL_1)
MDIO22 WRITE (B,LN3_LS_SERDES_CONTROL_2)
MDIO22 WRITE (B,LN2_LS_SERDES_CONTROL_2)
MDIO22 WRITE (B,LN1_LS_SERDES_CONTROL_2)
MDIO22 WRITE (B,LN0_LS_SERDES_CONTROL_2)
MDIO22 WRITE (B,LN3_LS_SERDES_CONTROL_3)
MDIO22 WRITE (B,LN2_LS_SERDES_CONTROL_3)
MDIO22 WRITE (B,LN1_LS_SERDES_CONTROL_3)
MDIO22 WRITE (B,LN0_LS_SERDES_CONTROL_3)
MDIO22 WRITE (B,HS_OVERLAY_CONTROL)
MDIO22 WRITE (B,LN3_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (B,LN2_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (B,LN1_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (B,LN0_LS_TP_OVERLAY_CONTROL)
MDIO22 WRITE (B,HS_TP_CONTROL)
MDIO22 WRITE (B,CLK_SEL_CONTROL)
MDIO22 WRITE (B,CLK_CONTROL)
MDIO22 WRITE (B,SKEW_CONFIG_CONTROL)
MDIO22 WRITE (B,HS_ALIGN_CODE_CONTROL)
MDIO22 WRITE (B,BIT_LM_CONTROL)
MDIO22 WRITE (B,LN3_LS_TXFIFO_CONTROL)
MDIO22 WRITE (B,LN2_LS_TXFIFO_CONTROL)
MDIO22 WRITE (B,LN1_LS_TXFIFO_CONTROL)
MDIO22 WRITE (B,LN0_LS_TXFIFO_CONTROL)
MDIO22 WRITE (B,LN3_LS_LOS_CONTROL)
MDIO22 WRITE (B,LN2_LS_LOS_CONTROL)
MDIO22 WRITE (B,LN1_LS_LOS_CONTROL)
MDIO22 WRITE (B,LN0_LS_LOS_CONTROL)
MDIO22 WRITE (B,LN3_DATA_SRC_CONTROL)
MDIO22 WRITE (B,LN2_DATA_SRC_CONTROL)
MDIO22 WRITE (B,LN1_DATA_SRC_CONTROL)
MDIO22 WRITE (B,LN0_DATA_SRC_CONTROL)
MDIO22 WRITE (B,LN3_LS_CH_CONTROL_1)
MDIO22 WRITE (B,LN2_LS_CH_CONTROL_1)
MDIO22 WRITE (B,LN1_LS_CH_CONTROL_1)
MDIO22 WRITE (B,LN0_LS_CH_CONTROL_1)
MDIO22 WRITE (B,HS_CH_CONTROL_1)
MDIO22 WRITE (B,VS_TX_MARKER_SEARCH_CHAR)
MDIO22 WRITE (B,VS_TX_MARKER_REPLACE_CHAR)
MDIO22 WRITE (B,VS_RX_MARKER_SEARCH_CHAR)
MDIO22 WRITE (B,VS_RX_MARKER_REPLACE_CHAR)
MDIO22 WRITE (B,VS_TX_IDLE_P_CHAR)
MDIO22 WRITE (B,VS_TX_IDLE_N_CHAR)
MDIO22 WRITE (B,VS_RX_IDLE_P_CHAR)
MDIO22 WRITE (B,VS_RX_IDLE_N_CHAR)

MDIO22 WRITE (B,VS_TX_SCR_CONTROL)
MDIO22 WRITE (B,VS_TX_SCR_SEED_CONTROL_1)
MDIO22 WRITE (B,VS_TX_SCR_SEED_CONTROL_0)
MDIO22 WRITE (B,VS_TX_SCR_POLY_CONTROL_1)
MDIO22 WRITE (B,VS_TX_SCR_POLY_CONTROL_0)
MDIO22 WRITE (B,VS_RX_DESCR_CONTROL)
MDIO22 WRITE (B,VS_RX_DESCR_SEED_CONTROL_1)
MDIO22 WRITE (B,VS_RX_DESCR_SEED_CONTROL_0)
MDIO22 WRITE (B,VS_RX_DESCR_POLY_CONTROL_1)
MDIO22 WRITE (B,VS_RX_DESCR_POLY_CONTROL_0)
MDIO22 WRITE (B,MC_AUTO_CONTROL)

//********************************************************************************************
//                            Issue Data Path Reset
//********************************************************************************************
WAIT(500)
MDIO22 WRITE (A,CHANNEL_CONTROL_1)
MDIO22 WRITE (B,CHANNEL_CONTROL_1)

MDIO22 WRITE FUNC (A,DATAPATH_RESET,0x1)
MDIO22 WRITE FUNC (B,DATAPATH_RESET,0x1)
MDIO22 WRITE FUNC (A,DATAPATH_RESET,0x0)
MDIO22 WRITE FUNC (B,DATAPATH_RESET,0x0)

// Wait 1000mS
WAIT(1000)

//********************************************************************************************
//                            Verify HS_AZ_DONE and LS/HS PLL Lock Status
//********************************************************************************************

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,CHANNEL_STATUS_1)
MDIO22 READ (B,CHANNEL_STATUS_1)

// Poll LS/HS_PLL_LOCK,HS_AZ_DONE
MDIO22 READ UNTIL (A,CHANNEL_STATUS_1,0x1003,0x1003,1000)
MDIO22 READ UNTIL (B,CHANNEL_STATUS_1,0x1003,0x1003,1000)

// Wait 100mS
WAIT(100)

//********************************************************************************************
//                            Clear Status Registers and Error Counters
//********************************************************************************************

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,CHANNEL_STATUS_1)
MDIO22 READ (B,CHANNEL_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LN0_LS_STATUS_1)
MDIO22 READ (A,LN1_LS_STATUS_1)
MDIO22 READ (A,LN2_LS_STATUS_1)
MDIO22 READ (A,LN3_LS_STATUS_1)

MDIO22 READ (B,LN0_LS_STATUS_1)
MDIO22 READ (B,LN1_LS_STATUS_1)
MDIO22 READ (B,LN2_LS_STATUS_1)
MDIO22 READ (B,LN3_LS_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,HS_STATUS_1)
MDIO22 READ (B,HS_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LT_LINK_PARTNER_CONTROL)
MDIO22 READ (B,LT_LINK_PARTNER_CONTROL)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LINK_PARTNER_STATUS)
MDIO22 READ (B,LINK_PARTNER_STATUS)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LT_LOCAL_DEVICE_STATUS)
MDIO22 READ (B,LT_LOCAL_DEVICE_STATUS)


// Read and Clear Error Counters
MDIO22 READ (A,HS_ERROR_COUNTER)
MDIO22 READ (B,HS_ERROR_COUNTER)

MDIO22 READ (A,LS_LN0_ERROR_COUNTER)
MDIO22 READ (B,LS_LN0_ERROR_COUNTER)

MDIO22 READ (A,LS_LN1_ERROR_COUNTER)
MDIO22 READ (B,LS_LN1_ERROR_COUNTER)

MDIO22 READ (A,LS_LN2_ERROR_COUNTER)
MDIO22 READ (B,LS_LN2_ERROR_COUNTER)

MDIO22 READ (A,LS_LN3_ERROR_COUNTER)
MDIO22 READ (B,LS_LN3_ERROR_COUNTER)


//********************************************************************************************
//                            Verify Channel Status
//********************************************************************************************

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,CHANNEL_STATUS_1)
MDIO22 READ (B,CHANNEL_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LN0_LS_STATUS_1)
MDIO22 READ (A,LN1_LS_STATUS_1)
MDIO22 READ (A,LN2_LS_STATUS_1)
MDIO22 READ (A,LN3_LS_STATUS_1)

MDIO22 READ (B,LN0_LS_STATUS_1)
MDIO22 READ (B,LN1_LS_STATUS_1)
MDIO22 READ (B,LN2_LS_STATUS_1)
MDIO22 READ (B,LN3_LS_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,HS_STATUS_1)
MDIO22 READ (B,HS_STATUS_1)



// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LT_LINK_PARTNER_CONTROL)
MDIO22 READ (B,LT_LINK_PARTNER_CONTROL)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LINK_PARTNER_STATUS)
MDIO22 READ (B,LINK_PARTNER_STATUS)

// Read and Clear Latched Status Register Bits
MDIO22 READ (A,LT_LOCAL_DEVICE_STATUS)
MDIO22 READ (B,LT_LOCAL_DEVICE_STATUS)



// Read and Clear Error Counters
MDIO22 READ (A,HS_ERROR_COUNTER)
MDIO22 READ (B,HS_ERROR_COUNTER)

MDIO22 READ (A,LS_LN0_ERROR_COUNTER)
MDIO22 READ (B,LS_LN0_ERROR_COUNTER)

MDIO22 READ (A,LS_LN1_ERROR_COUNTER)
MDIO22 READ (B,LS_LN1_ERROR_COUNTER)

MDIO22 READ (A,LS_LN2_ERROR_COUNTER)
MDIO22 READ (B,LS_LN2_ERROR_COUNTER)

MDIO22 READ (A,LS_LN3_ERROR_COUNTER)
MDIO22 READ (B,LS_LN3_ERROR_COUNTER)

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

     Hi, Markus! Thank you very much for your help!
     I made a mistake Yesterday. I measured PRBSEN pin on my board and it's always high. I changed a new one and my lane sucessfully shake hands. But when I transmit , the receive data is not correct .
     
     My configuration:
     <addr  =    data>
      0x1D  = 0x0000  (Disable HS marker search/replacement)
     
      Read Status Data:
     <addr  =    data>
      0x0F  = 0x1C27
      0x10  = 0x0000
      0x11  = 0x0000
      0x13  = 0x2140
      0x14  = 0x0040
     
      Q:Could you have some methods to confirm the problem of the device? or Which register should I try to change?
     
      PS:My data looks like left shift one bit , but I am not exactly sure! e.g. I transmit 0x88 , and receive 0x11.
     
      Best Regards
     
      ManU Li

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    to test if your transmission is working, you can use the TLK10022's inbuilt test patterns PRBS both for LS and HS. Therefor the PRBSEN Pin has to be set high!

    You can activate HS patterns by setting bits [13:12] in register 0x0B and choose a specific pattern by changing bits[10:8]. For the LS the same procedure applies in register 0x0A. Reading the Error Counter for LS and HS (read register 0x10 for will give you an indication, how good your setup is working. Please make in both cases sure, that you loop back your signals from TX to RX.

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

     Hi,
     Thank you for suggestion! I configed the device by your information, and the following are the test results：
     
     S1：  
      Configuration:
      <addr  =    data> 
       0x1D  = 0x0000  (Disable HS marker search/replacement)
       0x0B  = 0x3020 (enable HS_TP_GEN & HS_TP_VERIFY and select High Frequency Test Pattern)
       The other Registers : Default Value
      
      Read reg data：
      <addr  =    data>
       0x0F  =    0x9807
       0x10  =    0x0000
     
     S2：
      Configuration:
      <addr  =    data> 
       0x1D  = 0x0000  (Disable HS marker search/replacement)
       0x0A  = 0x3000 (enable LS_TP_GEN & LS_TP_VERIFY and select High Frequency Test Pattern)
       The other Registers : Default Value
      
      Read reg data：
      PRBS_PASS = '0';
        <addr  =    data>
         0x13  0xA944
         0x11  0x056E
        
     S3:
      Configuration:
      <addr  =    data> 
       0x1D  = 0x0000  (Disable HS marker search/replacement)
       0x0A  = 0x3100 (enable LS_TP_GEN & LS_TP_VERIFY and select Low Frequency Test Pattern)
       The other Registers : Default Value
      
      Read reg data：
      PRBS_PASS = '0';
        <addr  =    data>
         0x13  0x2844
         0x11  0xFFFF 
        
     S3:
      Configuration:
      <addr  =    data> 
       0x1D  = 0x0000  (Disable HS marker search/replacement)
       0x0A  = 0x3200 (enable LS_TP_GEN & LS_TP_VERIFY and select Mixed Frequency Test Pattern)
       The other Registers : Default Value
      
      Read reg data：
      PRBS_PASS = '0';
        <addr  =    data>
         0x13  0x2040
         0x11  0x06D3 
     S4:
     Configuration:
     <addr  =    data> 
      0x1D  = 0x0000  (Disable HS marker search/replacement)
      0x0A  = 0x3500 (enable LS_TP_GEN & LS_TP_VERIFY and select Mixed Frequency Test Pattern)
      The other Registers : Default Value
     
     Read reg data：
     PRBS_PASS = '0';
       <addr  =    data>
        0x13  0x2040
        0x11  0xFFFF 
     
     From the above information, my problem seems on low speed side. What could cause this problem? Signal Integrity? or Configuration?
      
     Best Regards
     ManU Li

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    your question is not so easy to answer, because I first have to understand the setup of your test system. Could you please upload a block diagram of your test setup? Have you tested all 4 of the LS lanes?

    From a first view of your test results it looks like a signal integrity issue, but as I mentioned before, to be able to help you better I need a little bit more Information. In register 0x08 you can change the equalizer for each LS lane by changing the bits [11:8].

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

    Hi, Markus!

            Let me add the test conditions. TX and RX of high speed side connect to a SFP+ , and I look back SFP+ by a fiber.I upload my Configuration steps.

    6320.My tlk10022 Configuration setup.txt 
    1.Init Device
   WRITE(GLOBAL_CONTROL_1,0x8610);    
   WRITE(GLOBAL_CONTROL_1,0x0610);    
   WRITE(LS_TP_OVERLAY_CONTROL,0x3000);
   WRITE(HS_CH_CONTROL_1,0x0000);
2.Wait 10ms
3.Read PLL Status
	READ UNTIL(CHANNEL_STATUS_1(1:0) == "11");(HS_PLL & LS_PLL Locked)
4.Datapath Reset
	WRITE(RESET_CONTROL,0x0008);
5.Read LS Lane Status
	WRITE(LS_SERDES_CONTROL_1,0x0115/0x1115/0x2115/0x3115);
	READ(LS_STATUS_1);
	READ(LS_LN_ERROR_COUNTER);
6.Repeat 5	

I can read status value by PC.


    Line rate of LS is 2.5G, whitch test pattern should I choose?

    My understanding:

          Data flow in LS test :     LS_TX_LANE -> HS_TX_LANE -> HS_RX_LANE -> LS_TX_LANE

          By the result , HS is the correct state , so HS_TX_LANE -> HS_RX_LANE is OK.  And my problem occurs in LS_TX_LANE -> HS_TX_LANE or HS_RX_LANE -> LS_TX_LANE , they are done by the chip , so my Configuration is wrong.

            My understanding is correct?

            Best Regards
            ManU Li

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

     

    for me it is still not completly clear how your system is set up. Please see the following questions:

    • Are you using a TI-Evaluation Board connected to your FPGA Board or is the TLK10022 already on a PCB with the FPGA?
    • How do you write/read the MDIO data to the device?
    • Did you also do a LS loopback just to see if the device's transmitter and receiver are working?
    • Which Channel are you using, A or B?

    The test pattern I would recommend to use is the PRBS7.

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

     Hi, Markus!


      To answer your questions:
           The TLK10022 is already on a PCB with the FPGA, and I don't have TI-Evaluation Board.
           I write/read the MDIO data to the device by FPGA, and the code is written by myself.
           Yes I did a LS loopback, and the FPGA's transmitter and receiver are working.
           I am using channel A ,and channel B is powered down. 
       
      Hs side is correct only in High Frequency Test Pattern , and Ls side is not correct in every Test Pattern.
      
      Best Regards
      ManU Li 

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    ok, I now understand your setup completely.

    When you are trying to send the PRBS7 pattern from LS TX via HS to LS RX you have to activate the bit interleaved mode of the TLK10022. This is done by setting Bits 8 & 9 in register 0x01. Byte interleaved mode is not working  because there is no bytewise test pattern the receiver can lock to.

    If this doesn't work, you might want to test the signal integrity from the FPGA to the TLK10022 and back. Activate therefor PRBS7 on the LS lines and mirror back the signal via the FPGA to the corresponding RX lines.

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

    Hi, Markus!
    I can reivce data corectly now, but the lane order is wrong...
    High speed lookback, and the lane order is 4 kinds.when borad power up ,lane order is one of the following four cases.

    tx: lane0 -> 0
    lane1 -> 1
    lane2 -> 2
    lane3 -> 3

    rx: lane0 -> 0 (corect)
    lane1 -> 1
    lane2 -> 2
    lane3 -> 3

    lane0 -> 1
    lane1 -> 2
    lane2 -> 3
    lane3 -> 0

    lane0 -> 2
    lane1 -> 3
    lane2 -> 0
    lane3 -> 1

    lane0 -> 3
    lane1 -> 0
    lane2 -> 1
    lane3 -> 2

    I enable link training (LT_ENABLE = '1') and disable marker search/replacement(RX_LANE_MARKER_EN = '0' ,TX_LANE_MARKER_EN = '0');
    status reg 0x0F = 0x1C07,0x14 = 0x0040;

    What should I do?

    Best Regards
    ManU Li

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    it is good to hear that you got it working now.

    Because I don't know what kind of data you will use in your end application:

    • In bitinterleaved operation (no 8 bit or 10 bit chunks of data) you have to get the order right via using the FPGA and sending a training sequence after start up.
    • If you will be using 8b/10b data in your end application, you can switch back to byteinterleaved operation and there will be no variation in lanes, when you enable TX_LANE_MARKER and RX_LANE_MARKER . (You can test this with the CRPAT test pattern and enabled 8b/10b encoding/decoding.)

    Link Training has no effect on the lane order.

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

     Hi, Markus!
      Thanks for your reply!
      
      I enable 8b/10b encoder and decoder on LS and HS.
      I enabled RX_LANE_MARKER_EN and TX_LANE_MARKER_EN.But receiving data is wrong periodically.
      I think my search marker character is wrong , but I don't know how to get the correct character.
      My starting data of lane0 is 0x4A4A , and before reaching the LS input pins it is 8b/10b encoded (0x4A = D10.2 = 0101010101).
      I tried to config VS_TX_MARKER_SEARCH_CHAR and VS_RX_MARKER_REPLACE_CHAR = 0101010101(D10.2) or 0001001010(0x4A) , and results were all wrong.
      What number should I config?
        
      Best Regards
      ManU Li 

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    you might only want to enable 8b/10b encoding for the LS first. You can still enable it for HS when everything else is working.

    The marker detection should already work, when you set  RX_LANE_MARKER_EN and TX_LANE_MARKER_EN. Use the default settings for VS_TX_MARKER_SEARCH_CHAR and VS_RX_MARKER_REPLACE_CHAR.

    Are you sending D10.2 on all four lanes or only lane 0 ?

    Best regards

    Markus Zehendner

  • 0 in reply to Markus Zehendner
    Prodigy 80 points

     Hi, Markus!
     Thanks for your reply!
      
    I enabled 8b/10b encoding for all of the LS and HS. My system is wrong when using  default settings for VS_TX_MARKER_SEARCH_CHAR and VS_RX_MARKER_REPLACE_CHAR.

    I am sending D10.2 on all four lanes , and I can change it.

    I don't know how to calculate the value for VS_TX_MARKER_SEARCH_CHAR , when I send 0x4a in my configuration.
      
    Best Regards
    ManU Li 

  • 0 in reply to manU li
    TI__Intellectual 1485 points

    Hi ManU,

    please verify that you have channel sync on the receiver side (check register 0x013 bit 8 for each lane).

    What you can try now is to use a different test character code on lanes 1-3. So the lane marker pattern is specific for lane 0, because the replacement is done after the serialization.

    Best regards

    Markus Zehendner