SN65LVDS302 SSC Compatible?

Hello Diego-san,

Thank you for your prompt reply.

I understand it does not support SSC.

Background to this question, it have an issue of the input CLK in the current product as you guessed.

We will not be able to change into other products from SN65LVDS302.

Thank you.

Best Regards,

H.Fujikawa

Diego-san,

I'm sorry for my late reply.

Please let me correct, it is not only the issue but also design change.

When we change PCLK 27MHz to 54MHz, should consider to improve EMI.

So our ASIC(Ser) sends the CLK forced SSC.

I attached the figure file about fCLK and fMOD.

Please advice and verify the allowable input fCLK range of PLL in SN65LVDS302.

Best Regards,

H.Fujikawa5810.SN65LVDS302_input_CLK.xlsx

Hi Fujikawa-san,

    I shared the clock information with the design team, but they also asked about the implemented de-serialization Mode. could you confirm this?

Best regards,

Diego.

Hello Diego-san,

Thank you for your confirmation.

I checked with my customer as follows.

・De-serialization Mode = 3ChM (LS1=1, LS0=0)

・D0 = Data 8-bit + VS

・D1 = Data 8-bit + HS + DE

・D2 = Dummy

・F/S Pin = 0 - slow output rise time

Thank you.

Best Regards,

H.Fujikawa

Hello Diego-san,

Thank you so much.

I appreciate you and your team.

Thank you.

Best Regards,

H.Fujikawa