Hi,
The MAC will be communicating to the phy in the following way:
1) RGMII for both 100Mbps and 1000Mbps.
2) We will be streaming data as fast as the link allows so the internal status registers of the PHY will be accessed very rarely. Probably after every 50 to 100 transactions.
3) We did not hook up the interrupt out of the phy to our MAC due to lack of pins.
I read the following in the datasheet
section 4.6.3 indicates "No glitch is allowed on the clock signals during clock speed transition".
I would like to know what the MAC is supposed to do in the following situation:
In the middle of the MAC doing a gigabit transmission to the Transmitter phy, the receiver phy is switched from a gigabit receiver to a 100Mbps receiver.
Since the clock speed/rate type of the transmission of MAC to phy is totally different in gigabit (125MHz ddr) vs 100Mbps (25MHz source synchronous sdr), I am afraid, that the phy might have an issue when it changes speed from gigabit to 100Mbps or vice versa with it's clock input toggling at the wrong speed.
Thanks for the help,
Amish
