Hi E2E,
I'd like to loop the output port AOUTP/N to BINP/N with an FPGA output driving AINP/N. AOUTP has a +1.3dB gain into BINP/N.
This is a basic loopback test, and Fig. 13 of the datasheet would indicate that this is safe. Are there any gotchas with this scheme?
Thanks.