DS80PCI800 / Datasheet Revision F,G

Hi Kato-san,

Originally, the DS80PCI800 RATE pin had an option to Tie a 1kOhm to VDD in order to force the output driver to behave as a linear Gen-3 buffer with de-emphasis. During the last revision, it was discovered that doing this also puts the Signal Detect function internally into a slow turn-on/turn-off mode to activate the channel. When the Signal Detect is in this slow mode, it causes the DS80PCI800 to violate the PCIe spec. Therefore, if you require the linear Gen-3 buffer, we recommend keeping the RATE pin as FLOAT.

Apologies for the confusion.

Thanks,

Michael

Michael - san,

Thank you for the explanation.

DS80PCI800 is used in our customer's Current Equipment as Gen3 with DEM.

If RATE pin is tied 1kohm to VDD,  do we have to persuade customer to change RATE pin setting ?  We won't be able to make it.

Best Regards,

Kato

Hi Kato-san,

For best performance, I recommend operating with RATE = F if possible. I believe this will be a savings on the BOM cost as well since they will be depopulating a resistor. Since the pin is now reserved, I would strongly suggest that they move in this direction if there is still time.

However, if the design you are talking about is already finished and fabbed, the link should still operate error free at Gen-3 even when RATE is tied via 1kOhm to VDD. If your customer is not concerned about the slower lag time needed for the link to become active (due to Signal Detect being in Slow Mode), they can still have the resistor tied via 1kOhm to VDD. For future projects moving forward, please recommend that for the final design, DS80PCI800 RATE = F.

Michael

Hi,

Thank you for the reply. For already finished and fabbed equipmets, customer has no choice but to leave RATE tied 1kohm to VDD.

So, would you please provide us with explanatory materials ?

Best Regards,

Kato

Michael - san,

We have to explain the issues to customer. so, could we discuss offline ?We need to understand it more detail.

Best Regards,

Kato