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DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver

Peter Gatchell
Intellectual 260 points

Hi,

The data sheet mentions "The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology." I would like to use this device as a clock fanout, driving with a 3.3V PECL on the input, at a rate of 250 MHz. Does "in excess of" mean that I can clock at the higher rate of 250 MHz?

Thanks.

  • 0
    TI__Expert 3175 points
    Hi Peter,
    I will refer you to the edge rate (rise and fall time) specification on page 5 and Figure 4. If we take a repeating 1-0 pattern, typ edge rate of 0.4ns is capable to support beyond 200MHz switching rate. However, the max edge rate of 1.5ns will put the limit to 200MHz. Above 200MHz, the output will be limited by the edge rate and could not reach its full amplitude.
    Here is how I did the calculation: edge rate of 1.5ns at 20-80%, so 100% is 2.5ns, with rising and falling edge becomes 5.0ns, or 1/5 = 200MHz.