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LMH1983 - Loss of Lock, Loss of Reference detection

Kawai
Guru 19785 points
Other Parts Discussed in Thread: LMH1983

Hello Team,

Could you please help us support LMH1983 about Loss of lock and Loss of reference detection ?

[Q1]
When the Lock is lost, would LOR be always High ?

[Q2]
When HIN is lacked for 1H pulse, would LMH1983 show Loss of lock and  Loss of reference at default setting ?
I believe LOCK will not be lost as LOCK1_Threshold is set to 8.
How about Loss of Reference ? Default value seems to be "1".

Best Regards,
Kawai

  • 0
    TI__Guru* 93670 points

    Hi Kawai-San,

    Please below note a deteiled explanation of how LOR works:

    When PLL is not locked, there is an internal counter that counts the number of 27MHz clock pulses between consecutive HSync pulses divide by two. This counter saturates at 0x7FFF(or 32767 decimal). Once this counter saturates we declare LOR. 

    On the other hand when PLL is locked and there is missing HSync pulses, we set LOR when the internal counter is greater than (Number of 27MHz clocks in one Hsync pulse + 3) X (LOR_THRES+1). 

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Guru 19785 points
    Hello Nasser-san,

    I' sorry that I could not understand the condition for LOR at PLL locked. Could you be more specific on this point "internal counter is greater than (Number of 27MHz clocks in one Hsync pulse + 3) X (LOR_THRES+1)." ?

    I also would like to clarify the Loss of Reference threshold REG 0x1B [2:0], I will post another question.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Guru* 93670 points
    HiKawai-San,
    When device is locked and auto format detection is enabled, the device has already determined the number of 27MHz clock within one HSYNC period. Let's call this number A for example. Given this, when we are locked and there is missing HSYNC pulse, we declare LOR when internal 27MHz counter is greater than (A+3) times (LOR_THRESH+1).
    Regards,,nasser