Customer already designed to use both DS92LV18 and SN65LVDS250 like below.
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FPGA SERDES Cross-point Switch SERDES FPGA
Lattice >>> DS92LV18 >>> SN65LVDS250 >> 1m >> DS92LV18 >> Lattice
ECP2M ↑ Cable distance ECP2M
※60MHz clock (=1.2Gbps)
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Customer asked us "Is there any simulation data or guideline of cable distance/attenuation value at SN65LVDS250 output?"
In case of SERDES(DS92LV18), we already explained your application report(snla112e), Figure.3 to them.
Even though happened 3db loss at after 1m cable distance receive at SERDES, 1.2Gbps transfer rate still have about 2-3m allowance using CAT5e cable.
But, above scenario must be directly connected SERDES each. Once SN65LVDS250 placed in the middle of two SERDES,
it would be different scenario they think.
SN65LVDS250 min. Vod=247mV, DS92LV18 min. voltage swing(VTH-VTL)=200mV.
So, customer design looks like 47mV margin.
Do you have any advice about how to expect more than 47mV loss situation at SN65LVDS250 Output??
Best regards,
Satoshi
