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LMH0044 Equalizer Jitter Transfer and Jitter Tolerance

Mark Heh
Intellectual 270 points
Other Parts Discussed in Thread: LMH0044, LMH0041, LMH0318

The LMH0044 datasheet states that it can equalize up to 200 meters of Belden 1694A at 1.485 Gbps. The jitter for various cable lengths (with equalizer pathological) are stated a table.

At 140 meters of Belden 1694A cable, the typical jitter is 0.25 UI. At 200 meters of the same cable, the typical jitter is 0.30 UI. This is the output timing jitter right?

Since 200 meters - 140 meters = 60 meters and 0.30 UI - 0.25 UI = 0.05 UI, every 60 meters of Belden 1694A cable has roughly 0.05 UI of jitter?

Thus, 200 meters of cable has: 200 meters / 60 meters = 3.33 * 0.05 UI Jitter = 0.17 UI Jitter.

Thus, the rest, 0.30 UI - 0.17 UI = 0.13 UI jitter is intrinsic to the device?

Since SMPTE 292 specs the max timing jitter as 1 UI, jitter is not the limiting factor preventing the device from equalizing Belden 1694A cable longer than 200m. is the limiting factor the losses in the cable and the device's equalization ability. What is the maximum jitter the input of the LMH0044 can tolerate? Will the output jitter remain the same?

The link is shown below. I am looking to understand the jitter budget of my system, which entails understanding the jitter transfer and alignment of the LMH0044. We are neglecting jitter associated with other unlisted cables, connectors, and PWB traces. I'm looking at understanding how much jitter budget I have left in the system for a transformer or other device (X in figure below).

Could you help me understand? Also, does the reclocker eliminate all the alignment jitter?

  • 0
    TI__Guru* 93670 points

    Hi Mark,

    1). Jitter noted in the LMH0044 vs cable length is the total jitter or it is both low and high frequency.

    2). LMH0041 reclocker loop bandwidth is in order of MHz(~1.5MHz at HD) and thus it attenuates the high frequency jitter above 1.5MHz at 20dB per octave.

    3). LMH0041 tracks jitter within it's loop bandwidth(1.5MHz).

    LMH0041 Jitter tolerance is 0.6UI and this is the high frequency(above loop bandwidth) jitter tolerance. If we assume all of the jitter you have noted is above LMH0041 loop bandwidth, given your example, it means you have about a quarter of UI or 0.24UI of eye opening margin before we hit LMH0041 jitter tolerance.

    Regards,,nasser

     

  • 0 in reply to Nasser Mohammadi
    TI__Mastermind 29655 points
    Hi Mark,

    To add to Nasser's response, the LMH0044 is a cable equalizer, so it will only apply frequency-dependent gain to help reverse the effect of attenuation loss that naturally occurs when running high-frequency data over long cable lengths.

    The typical jitter is the total jitter at the output of the LMH0044 after the cable equalizer, and the cable equalizer does not discriminate between attenuating low frequency or high frequency jitter, hence why we cannot specify output timing jitter and alignment jitter.

    The LMH0041, which has an internal CDR, will act to help minimize the alignment jitter seen at the output of the LMH0041, but your jitter budget before the LMH0041 is determined by the LMH0041's jitter tolerance (0.6 UI) for input jitter frequencies less than f3 according to SMPTE RP184.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Intellectual 270 points
    Thank you for adding to Nasser's response.

    Why is the LMH0318 IN0, IN1, and OUT1 considered "Analog" in the datasheet's Pin Descriptions Table under the I/O column? OUT0 is considered "CML Compatible." I thought the SDI signals are considered digital.
  • 0 in reply to Mark Heh
    TI__Mastermind 29655 points
    Hi Mark,

    You are correct that SDI signals are considered digital as far as the data that they contain. We listed them as analog in our datasheet since we perform analog processing to condition the input and output signals and improve the analog quality so that they can be interpreted correctly in the digital domain (for example, SMPTE-compatible rise/fall times, amplitude levels, and output jitter).

    Listing the pins as "analog" is a means of differentiating these pin functions from those used for purely digital logic such as the LOCK pin or ADDR[1:0] pins.

    Thanks,

    Michael