Part Number: DS90UH929-Q1
Other Parts Discussed in Thread: DS90UH940-Q1, DS90UH926Q-Q1, DS90UH928Q-Q1
Hi,
I would like you to confirm about restricition for input PCLK of DS90Ux929.
According to datasheet, there is following section.
8.4.2 FPD-Link III Single Link Operation
The DS90UH929-Q1's single link mode transmits the video over a single FPD-Link III to a single receiver. Single
link mode supports frequencies up to 96MHz for 24-bit video when paired with the DS90UH940-Q1/DS90UH948-
Q1. This mode is compatible with the DS90UH926Q-Q1/DS90UH928Q-Q1 when operating below 85MHz.
From above, I understand that user can input up to PCLK=96MHz when they use Ux94x as DES.
However, I'm concerned about there is any input jitter restriction in this case.
I understand that general Ux92x device(925,6,7,8) can use up to PCLK=85MHz. And input jitter spec is defined as 0.4UI at SER.
However, in case of Ux929, although maximum PCLK is defined over Ux925,927, input jitter spec is relaxed (defined as 0.3UI(tmds)).
So, I suspect that there is any restriction when user use high pclk frequency. Or, does only Ux929 have jitter cleaner in device ?
Could you clarify although maximum pclk of Ux929 is over other 92x(x=5,6,7,8), why input jitter of only Ux929 is relaxed than other 92x deivce ?
Thanks in advance,
Machida
