SN65LVDS94: SNLVDS94 data output pins

Amitai Broyde

Part Number: SN65LVDS94

Does SHTN pin cause the SN65LVDS94 data output lines to become HiZ? can I use that feature to connect two parts in parallel?

over 7 years ago

0 Joel Jimenez0 over 7 years ago

TI__Mastermind 18655 points

Hello Amitai,

Yes, it is a suitable implementation. Since a low-level on SHTDN places the TTL outputs in a high-impedance state. Just, consider the "Enable time, SHTDN to phase lock" and the "Disable time, SHTDN to Off state".

Regards,
Joel

0 Nir Flysher over 7 years ago in reply to Joel Jimenez0

TI__Expert 3287 points

Dear Joel,

a. Does your answer relates also for the CLK as well - meaning is it also HiZ when the SHTN pin is enabled ?
b. Does this HiZ set on power-up or do the D0-D28 & Clock out are set to a specific level on power-up ?

Regards,
Nir.

0 Amitai Broyde over 7 years ago in reply to Joel Jimenez0

Prodigy 30 points

Thanks,

Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

Interface

Interface forum

SN65LVDS94: SNLVDS94 data output pins