Part Number: DP83867E
Hi,
I am looking into adding fail-safe bias resistors on the receiver end into an FPGA, to ensure that we have valid clock and receive data into the FPGA, when the PHY isn’t turned on. This equates to about a ~110mV differential DC bias to a logic ‘0’ in a nominal case with our current implementation.
What are the output specifications of the LVDS drivers when operating in SGMII mode? I would like to make sure that the output differential voltage will be sufficient to overcome the DC bias we have put on our LVDS Receive pairs going to our FPGA.
Thank you.
