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LX16EVK01: GPIO vs DIN

Uladzislau Maiseichykau
Prodigy 40 points
Part Number: LX16EVK01

Hello,

I am working with the LX16EVK01-Rx (Deserializer) and the LX16EVK01-Tx (Serializer) boards. I am using all 18 pins of the Serializer/Deserializer pins, but measure a latency on the GPIO0 pin relative to the other DIN pins. I have tied the GPIO 0, Din 0, and Din 1 pins together on the Serializer. Since the three input pins are tied, I would expect that the outputs at the Deserializer would be matched, however they are not. The GPIO0 output, is found 20 ns after Din 0 and Din 1. Do the GPIO pins work differently? Thank you and have a wonderful day.

  • 0
    TI__Intellectual 2915 points
    Hi,

    Can you tell us the purpose of this experiment? The GPIO switching freq is 66KHz where DIN pins are at PCLK. What are the status of LOCK and PASS pins at the Deserializer?

    Dennis
  • 0 in reply to Dennis Wu
    Prodigy 40 points

    Quote from datasheet:

     

    > 

    The GPIO maximum switching rate is up to 66 kHz when configured for communication between Deserializer GPI to Serializer GPO. Whereas data flow

    configured for communication between Serializer GPI to Deserializer GPO is limited by the maximum data rate of the PCLK.

    > 

     

    We are using it in the latter configuration and *should* get GPIO data at rate of PCLK. We see an apparent shift of 1 period of PCLK, which is running at f=50 MHz (T=20ns). The signal on GPIO trails the signal on DIN0 by ~ 20ns.

  • 0 in reply to Dennis Wu
    Prodigy 40 points
    Hello Dennis,

    I forgot to mention in my previous reply that the Lock and Pass lights are on. Do you have any other questions? Thank you and have a wonderful evening.
  • 0 in reply to Uladzislau Maiseichykau
    TI__Intellectual 2915 points
    It's possible there is a latency between GPIO and DIN. GPIO and ROUT[13:0] have different output latch circuitry in the deserializer. However, you should see no latency issue on ROUT[13:0], HSYNC, and VSYNC.

    What is your end application? Can you tell us the purpose of this experiment?

    Dennis
  • 0 in reply to Dennis Wu
    Prodigy 40 points
    Hello Dennis,

    We are using an 18-bit wide data bus and would like to transfer data over the serializer/deserializer at 50 MHz.
    We currently compensate for the ~20ns delay on GPIO0 and GPIO1 by moving those signals 1 PCLK period earlier on the serializer side. If this is a robust and technically sound solution, then we will keep this design into our final design. However, if this is not a recommended design practice, and we are using the serializer not as it was intended, we need to find another solution for transmitting our data.

    - Ulad
  • 0 in reply to Uladzislau Maiseichykau
    TI__Intellectual 2915 points
    Hi Ulad,

    Sorry I should have asked this before. Can you send the input pattern and scope waveforms that show 20ns delay on GPIO and DINx? I am thinking the GPIO and DINx have different IO circuitries and there is a delay. Do you see 1 cycle delay if PCLK changes to 25MHz or other frequencies from 50MHz?

    Dennis