DS90UB928Q-Q1: Question about Power-up sequence

Hi Fujihara-san,

Q.1) Does DS90UB928 have power-on-reset functionality?
Control registers are reset when PDB is toggled low. PDB must be held low for a minimum of 2ms.

Q.2) Regarding to “VDD33 delay time”, Table 10 defines it 0ms as lower limit.
If VDD33 ramps up faster than VDDIO, what negative effect is expected on the device?
Will it cause the permanent damage on the device?

If VDD33 and VDDIO are supplied separately, it is recommended that VDDIO should ramp 100us prior to VDD33. The minimum limit in Table 10 is 0ms because these supplies can be tied together and ramped simultaneously. I need to discuss with my design team if this will cause any damage, at a minimum it could cause the device to power-up in an unknown state.

Regards,
Ryan

Hi Ryan-san,

 

Thanks for your reply.

 

For Q.1, I would like to confirm below.

Device does not have automatic reset functionality when device power-on.

Therefore internal registers and other modules are in unstable state after power-on,

PDB toggling is required to make device in stable state.

Is my understanding correct?

 

For Q.2, please confirm with design team, I will wait for the feedback.

 

Best regards,

Nobuo

Hi Ryan-san,

I got further questions from customer.

Regarding Q2, customer asked what exact negative effects would be assumed by violating power-up sequence between VDDIO and VDD33.
Could you list up assumed ones?

Best regards,
Nobuo

Hello,

Sorry for additional question.
There is no description about VDDIO and VDD33 power-down sequence.
No special care for power down sequence?

Best regards,

Hi Ryan-san,

Thanks for the answers.

Customer asked further question about accuracy of 200MHz built-in RC oscillator.

Would you provide this information?

 

Best regards,

Nobuo Fujihara

Hello,
This question seems unrelated to the original thread. Could you please create a separate thread so it can be addressed properly by the right experts?