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DS90CF388: Ouput Clock is not stable

Jason Shen
Intellectual 1955 points
Part Number: DS90CF388

Dear team

Right now the display system is sometime work, but sometime not work. when not work, the pixel is shifted. and we check the device, find the clock output have two frequency after analysis, does this normal? liek input frequency 69.25MHz and 58ps jitter. but the output have two frequency like 69.58Mhz and 68.7Mhz. seemed the PLL have some probelm.

so with normal working, our device will have same output clock as input, right? if not, is there some way to oppotimized the PLL?

Thanks for the hlep.

Jun Shen

  • 0
    TI__Intellectual 1635 points
    Hi Jun,

    You are correct, that the output clock will be the same frequency as the input clock when the device is operating correctly. Have you observed the input clock to the DS90CF388 when the display is not working correctly? What is driving the input of the DS90CF388? Please ensure this is providing a clean clock. In addition, please ensure you have a clean power supply as well, as this can affect the communication link.

    Regards,
    Ryan
  • 0 in reply to Ryan Hashimoto
    Prodigy 60 points
    HI Ryan,

    Based on your answer above,I test the chip separately.The chip welding on an empty PCB, only provide power and the input clock and the input clock matching resistance, all of the power supply with dc voltage source. The input clock generated by FPGA LVDS function, the clock stability only 13 ps jitter, there are four input clock frequency 50 MHz, 60 MHz, 65 MHz and 69.5 MHz. Test the output clock is still two frequency as Jun Shen's description.

    I can not find the reason why there are two frequencies now. May I ask you any suggestions?

    Regards,
    Jian Wang