Part Number: TCA9534A
Team,
Customer is using this chip, we are wondering about the behavior on the port pins in terms of noise immunity/hysteresis, debounce situations, etc. The datasheet shows a VOH, and an IOL, which is a bit confusing.
Thanks!
Brian
Hey Brian,
The device's output is controlled by two FETs seen below:
The port pins DO NOT have any type of filtering/noise-immunity/EMI suppression, debounce features. It is just a push pull architecture that either pulls high (Q1 FET) or pulls low (Q2 FET).
To try to ease the confusion, looking at section 6.5 of the datasheet where P Port VoL=0.5V means if you pull low (set the output to low) and probe the pin and see the Voltage is 0.5V (not fully GND) then a minimum of 8mA is flowing into the port. From this you can back calculate the Ron of the FET knowing the current and the voltage.
On a side note our SDA/SCL does have a glitch filter internally (supresses glitches of 50nS).
Thanks,
-Bobby
