I wonder if you could help me with an issue I'm seeing accessing some of registers in the TLK10031 - when operating in Clause 45 MDIO mode.
We are using the TLK10031 to convert from XAUI to XFI (10GBASE-R). We have a Marvell 88E6390X 10G Ethernet switch, where port 9 needs to be 10GBase-R. Unfortunately said switch does not support XFI (10GBASE-R) - only RXAUI and XAUI - so we're using the TLK10031 to convert from XAUI toi XFI.
To complicate matters more, we're using a Marvell Armada 38x processor for management, however the MDIO/MDC port only supports Clause 22 MDIO mode.
My understanding from reading the data sheet and from Table 7-2 that to operate in 10G-KR mode, on the rising edge of reset, the ST and MODE_SEL pins both need to be 0 - which is what we're doing :
With both ST and MODE_SEL set to 0, the only way of accessing the registers is in Clause 45 mode. However the processor only supports Clause 22 mode, so to circumvent this incompatibility we've routed the MDIO/MDC pins from the processor and the TLK10031 into a FPGA. We have written a state machine in the FPGA which allows us to generate Clause 45 frames to the TLK10031 (which is a two phase protocol) when we write the op, PhyAddr, DevType and addr/data to some FPGA registers from the processor - using Clause 22 mode :
https://www.totalphase.com/support/articles/200349206-MDIO-Background#clause45.
We have this working of a sort. We are able to read from the PMA/PMD registers using DevType 1 (details are on page 91 of the datasheet), the PCS registers using DevType 3 (see page 115) and the Auto-Neg registers using DevType 7 (see page 123) as shown below :
The syntax of the cl45_dbg++ command is as follows :
Usage: ./cl45_dbg++ r [port/phy] [device] [addr] [num]
For this board the TLK10031 is mapped to PHY address c.
However, I see some odd behaviour that I cannot understand from the datasheet. In particular, although I can access DevType 1, 3 and 7 (PMA/PMD, PCS and ANEG) register banks using clause 45, I seem unable to access DevType 0x1e (Vendor Specific Registers) :
If I look at the MDIO/MDC pins on a scope when accessing DevType 0x1e, everything looks fine to me, except that the TLK10031 is not driving the MDIO during the last 16 clock cycles :
Compare this when reading DevType 0x07 (AutoNeg) register 0 - see below. The second screenshot shows 0x3000 being driven onto MDIO by the TLK10031 during the last 16 clock cycles - which is correct if you consult Figure 7-151 in the datasheet.
There are some other observations that I've made. They are as follow:
1. The TLK10031 seems to require 33 preamble clock cycles.
2. Reading DevType 0 and 1 returns the same register set.
3. Reading DeType 2 and 3 returns the same register set.
4. Reading DevType 4 and 5 returns all FFs.
5. Reading DevType 6 and 7 returns the same register set
6. Reading DevType 8 to 0x1f returns all FFs.
Could you confirm if the above observations are correct, and can you provide any assistance with reading the Vendor registers (DevType 0x1e) please
