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Original question:

SN65HVD23: Propagation delay (SPRAC35)

SN65HVD235: CAN Sampling and Sync

Henrique T.
Intellectual 490 points
Part Number: SN65HVD235

I'm a beginner on interfaces and networks. I have some questions about  CAN synchronization and bit sampling. 

To do the Resynchronization, I understand that the nodes need to get the bus state outside the sampling point, to know if there is a phase error. 

So, do the nodes continuously monitor the status of the bus  (just like the inputs of a flip flop)? if yes, "what is the point of Sampling Point"?

Can I think this way:  Although the bus is continuously monitored, only the state during the sampling point is taken as valid value?

If yes, its because there may be many changes on the bus state inside a Bit Time, but outside the sampling point, due to phase errors between the nodes and only at the sampling point (in expected conditions) the bus state is stabilized and  the nodes are synchronized so the state is the correct one?

  • 0
    TI__Guru 62920 points
    Henrique,

    Yes, your understanding is correct. The CAN controller will "oversample" the RXD line by some amount that is determined by the controller's reference clock rate and timing configuration. This divides the bit time into a series of shorter periods called time quanta. This allows for a sampling position to be defined by the user at some position within the bit period (i.e., by defining it to be a certain number of time quanta after the start of the bit). The data is considered valid at the sampling point rather than immediately following an edge to allow for some propagation delays and settling time. (Also, of course, any consecutive bits of the same state would not result in an edge transition and so the receiving node does need to keep track of how long each bit is expected to be and and sample them accordingly.)

    Please let me know if any of this is not clear.

    Regards,
    Max
  • 0 in reply to Miguel Robertson
    Intellectual 490 points
    Thank You.
    Just the last sentence (in parentheses) I didnt understand very well. The part "any consecutive bits of the same state would not result in an edge transition" is OK.... but I didnt get this: "so the receiving node does need to keep track of how long each bit is expected to be and and sample them accordingly"
  • 0 in reply to Henrique T.
    TI__Guru 62920 points
    I was just trying to make the point that even with continuous monitoring of the bus, there will be no detectable activity for several bit periods if the bus had multiple dominant or recessive bits in a row. So, the controller needs to sample the bus state at fixed intervals to convert it into a series of bits.

    Max
  • 0 in reply to Miguel Robertson
    Intellectual 490 points

    I think I got...

    Even though the bus is "quiet", a message bit may be being transmitted. In this case no re-synchronization is performed but the Sampling Point does its job, translating the bus state into a message bit.

    Correct?

  • 0 in reply to Henrique T.
    TI__Guru 62920 points
    Yes, that's right.

    Good luck in implementing your CAN interface, and please feel free to post questions here whenever you need help clarifying your understanding.

    Max