Dear Team,
My customer is considering the SN65LVDS93 for a new design.
They're using a clock of 40MHz and have a measured jitter across all temperature of 55psec.
On the datasheet p.6 you mentioned you've tested the device with a clock of 50psec however there is no definition for the clock jitter requirements for the device.
Can you please clarify what are the clock jitter requirements for clock of 40MHz ?
Regards,
Nir.