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SN65LVDS93: Clock jitter limits

Part Number: SN65LVDS93

Dear Team,

My customer is considering the SN65LVDS93 for a new design.

They're using a clock of 40MHz and have a measured jitter across all temperature of 55psec.

On the datasheet p.6 you mentioned you've tested the device with a clock of 50psec however there is no definition for the clock jitter requirements for the device.

Can you please clarify what are the clock jitter requirements for clock of 40MHz ?

Regards,

Nir.

  • Hi Nir,

    There aren't any specifications for input clock jitter requirements for this device. Those values are just conditions under which the device was tested. Also, the SN65LVDS93 is quite an old device. They should consider switching to the SN65LVDS93A.

    Regards,
    I.K.
  • Hi I.K.

    Thanks for your quick response.
    Just to make sure I understand this correctly - does the device will have the same performance if we use a clock with jitter of 500psec as well ?
    As I understnad this the device has an internal PLL that generates the high freq for the serializer. Doesn't it have any requirements on the input frequency jitter ? Isn't there any jitter value that might break the PLL lock ?

    Can you please clarify ?

    Regards,
    Nir.
  • Hello I.K & Nir

    1. My source clock has the following jitter (measured):
    Integrated Phase noise over 12KHz-20MHz deliver jitter level of ~55ps RMS.

    Datasheet of SN65LVDS93A contains Jitter graph (p.11).
    2. Can i use this graph to evaluate SN93LVDS93 Jitter performance ?

    Both datasheets ('93 , '93A) define the Jitter magnitude of test condition (note 2 p.6 , p.9).
    3. What is the Jitter RMS level? (How to convert from magnitude to RMS)?

    Test condition of '93A has input clock jitter < 25ps , while '93 has input clock jitter < 50ps.
    4. Does '93A device is more susceptible to jitter than '93 ?

    Thank's

    Yaron
  • Dear IK,
    Can you please advise regarding Yaron's questions above ?
    1. Can we use the graph from the SN76LVDS93A (no A suffix) to evaluate the jitter performance for the SN65LVDS93 (without the A suffix).
    In other words - do they have the same jitter performance ?
    2. In the datasheet you're defining the jitter magnitude. We're familiar with RMS jitter. Can you please explain what is the meaning in jitter magnitude ? or how to convert from 'magnitude' to RMS jitter ?
    3. We're interested to understand whether the SN65LVDS93A is more sensitive to clock jitter ?
    4. Can you please describe in short what are the main differences between the SN65LVDS93 and SN65LVDS93A ?

    Regards,
    Nir
  • Hi Nic,

    Sorry for the delay. I am on international travel so responses will be delayed. The SN65LVDS93 and SN65LVDS93A are different dies so I don't believe you can use the same graph to evaluate jitter performance. The main difference between the 93A and the 93 is the clock frequency range. You can reference this document or other documents from the web for jitter conversions: www.idt.com/.../815-understanding-jitter-units

    Regards,
    I.K.