SN65DP159: In DisplayPort to DisplayPort Retimer Mode, Disparity Errors Only Accumulating on Lane 0 BERT_CNT[11:0] Counter

KT

Please refer to this note for DP159 pattern generator and verification, each lane has its own BERT error count. www.ti.com/.../sllu294.pdf

Thanks
David

Hi David,

1. Our setup is Host => DP159 => FPGA. DP159 is used in X-mode. I am trying to use DP159 disparity counters for all four lanes. We also use all four lanes of disparity counters in FPGA Rx. The problem I observe is the following:

a. Errors on lane 3 are detected at lane 3 of FPGA but lane 0 of DP159 and not at lane 3 of DP159.
b. Errors on lane 2 are detected at lane 2 of FPGA but lane 0 of DP159 and not at lane 2 of DP159.
c. Errors on lane 1 are detected at lane 1 of FPGA but lane 0 of DP159 and not at lane 1 of DP159.

2. The sllu294.pdf app note does not have any setup or info on configuration for disparity error monitoring.

Regards,
KT

KT

Are you following this programming guide?

(0xFF, 0x00); // Select Page 0
(0x0B, 0xXX); // Set TMDS_CLOCK_RATIO_STATUS to 1/10 for HDMI 1.4B and 1/40 for HDMI 2.0 data
rates
(0x0A, 0xB7); // Set to retimer mode and apply changes
(0x10, 0x01); // Select PRBS7 as the pattern
(0x0E, 0x07); // Load pattern verification on lanes 0 thru 2 when SWAP disabled, leave the clock
lane
//(0x0E, 0x0E); // Load pattern verification on lanes 1 thru 3 when SWAP enabled, leave the clock
lane
(0x0E, 0x00); // Load is latched

Can you please your a,b,and c statement?

Thanks
David

Hi David,

No, we are NOT following in the programming guide example because:

1. We are using DP159 in X-mode as DisplayPort to DisplayPort retimer. HDMI is NOT used.
2. We are NOT using PRBS7. We are monitoring for disparity errors of incoming DisplayPort 8b10b data using DP_TST_SEL[2:0] set to b000.
3. Can you please confirm what your request is for "Can you please your a,b,and c statement?" ? Appears to be missing a word.

KT

KT

Sorry for the typo, would you please clarify your statement?

a. Errors on lane 3 are detected at lane 3 of FPGA but lane 0 of DP159 and not at lane 3 of DP159.
b. Errors on lane 2 are detected at lane 2 of FPGA but lane 0 of DP159 and not at lane 2 of DP159.
c. Errors on lane 1 are detected at lane 1 of FPGA but lane 0 of DP159 and not at lane 1 of DP159.

Are you also loading the pattern verification?

(0x0E, 0x07); // Load pattern verification on lanes 0 thru 2 when SWAP disabled, leave the clock
lane
//(0x0E, 0x0E); // Load pattern verification on lanes 1 thru 3 when SWAP enabled, leave the clock
lane
(0x0E, 0x00); // Load is latched

Thanks
David

Hi David,

1. Regarding clarification of a,b,c statements: I enabled disparity error counting in the DP159 and in the FPGA. I forced bit errors upstream of the DP159 Rx on each of the four Rx lanes but only ever see DP159 BERT_CNT[11:0] for lane 0:

Disparity errors on physical lane 0 are reported on DP159 lane 0.
Disparity errors on physical lane 1 are reported on DP159 lane 0.
Disparity errors on physical lane 2 are reported on DP159 lane 0.
Disparity errors on physical lane 3 are reported on DP159 lane 0.

At the same time:
Disparity errors on physical lane 0 are reported on FPGA lane 0.
Disparity errors on physical lane 1 are reported on FPGA lane 1.
Disparity errors on physical lane 2 are reported on FPGA lane 2.
Disparity errors on physical lane 3 are reported on FPGA lane 3.

Why is the DP159 reporting disparity errors on any lane as disparity errors on lane 0 (BERT_CNT address 0x18, 0x19) ?

2. I have tried loading the pattern verification but that does not change behavior or fix problem. I tried the tried the following three configurations:
a. Set register 0x0e to value 0x0f, then set value to 0x00.
b. Set register 0x0e to value 0x07, then set value to 0x00.
c. Set register 0x0e to value 0x0e, then set value to 0x00.

Regards,
KT

KT

Thanks for your clarification. This is the expected behavior. DP159 can check for errors in PRBS pattern or 8b10b. If DP159 is in 8b10b error checking mode, errors from all lanes are lumped into a single register. For PRBS pattern, error for each lane is individually counted into separate registers.

Thanks
David