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Original question:

DS25BR120: DS25BR120 Transmission Characteristics

DS25BR120: Pre-Emphasis and the signal buffering

Michael T Schneider
Expert 3780 points
Part Number: DS25BR120

Hello Team, 

I have a customer with the below question that I was hoping to get an answer for. 

Currently the customer's design is using a 100 MHz clock on the IN+ and a 0 volt signal on the IN-. When looking at the output in this particular configuration OUT +/- appears as if the signal is buffered to kill oscillation. When making IN- the opposite of IN+ meaning 100 Mhz not, the outputs appear a bit cleaner.

Could you please explain more about this?

Thank you!

-Mike

  • 0
    TI__Mastermind 43795 points

    Hi Michael,

    How is the customer setting the common mode of the 100MHz clock signal?

    What is the signal amplitude?

    LVDS inputs are designed to have the input common mode supplied by the connected output, so this type of unbalanced signal can result in unexpected behavior.

    Regards.

    Lee