Other Parts Discussed in Thread: SN65LVDS100
Hi there,
We are looking to use SN65CML100 to recover our ac coupled, high speed CML logic (960Mbps) from long cable loss (3m). The eye diagram of the input looks like below, and it is almost closed.
For SN65CML100, we are not sure how low input swing (Vp-p) it could accept, or its sensitivity, given our little eye opening. The datasheet mentioned max positive-going differential input voltage threshold of 100mV. But it is not clear to us what would be the case if the input differential swing is below 100mV, as the datasheet is pretty short in length, compared to SN65LVDS100. I understand there is 25mV hysteresis, but I am not sure how much it is going to help.
In 10.3.1.2 of SN65LVDS100 datasheet, it has the words “When the input signal falls in this –100 mV < VID < 100 mV range, the receiver output state cannot be determined unambiguously. ”. Is that also true for SN65CML100?
Thanks,
Dawei
